Le Ye

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps

This paper presents a generic-purpose solution of highly power-efficient active-RC filters, which is suitable for analog baseband with wide bandwidth-range from several mega-Hz to hundreds of mega-Hz in wireless receivers. A 260 μA 7-20 MHz 6th-order active-RC low-bandwidth low-pass filter (LBW-LPF) and a 2.3 mA 240-500 MHz 6th-order active-RC high-bandwidth low-pass filter (HBW-LPF) are implemented in a standard 0.18 μm CMOS process to demonstrate this versatile solution. Highly power-efficient push-pull opamps with 30-to-35 dB gain are adopted for the filters, which allow us to focus on extending the bandwidth and reducing the power consumption. The push-pull opamp with adaptive-biased and pole-cancellation push-pull source follower (APP-SF) as the buffer stage is proposed to greatly reduce the power consumption and effectively extend the bandwidth. An adaptive bias mechanism is also proposed to tolerate the PVT variations for the opamps. In addition, the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation. The LBW-LPF only consumes 260 μA current from 1.8 V supply, achieves 14.4 dBm in-band IIP3 and 66.2 nV/√ Hz IRN density, and occupies 0.21 mm 2 silicon area without pads. The HBW-LPF merely dissipates 2.3 mA current from 1.8 V supply, achieves 11.3 dBm in-band IIP3 and 13.1 nV/√ Hz IRN density, and occupies 0.23 mm 2 silicon area without pads.

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65- nm CMOS

A highly reconfigurable merged analog baseband (MABB) with not only tunable bandwidth (BW), gain, and order but also reconfigurable power, noise, and linearity is proposed for multistandard integrated wireless receivers in this brief. The MABB could arrange the total gain to different stages for noise and linearity tradeoffs by introducing the merged biquad topology. To save power, the operational amplifier (Opamp) for the proposed MABB can reduce the GBW, as long as it meets the GBW requirement for different BW, gain, and order. A flexible power-efficient high-GBW Opamp with an adaptive common-mode bias circuit is also proposed for the eighth-order active-RC MABB. The proposed MABB covers a cutoff frequency range from 200 kHz to 20 MHz, whereas the gain could be tuned between 0 and 72 dB. The proposed highly reconfigurable MABB is suitable for multistandard integrated wireless receivers.

A 2.3mA 240-to-500MHz 6 th -order active-RC low-pass filter for ultra-wideband transceiver

This paper presents a 6th-order active-RC low-pass filter with 240 MHz to 500 MHz tunable bandwidth, which is suitable for the ultra-wideband transceivers. The filter consumes only 2.3 mA from 1.8 V supply voltage, which is mainly attributed to the proposed highly power-efficient operational amplifier (Opamp) with an adaptive-biased pole-cancellation push-pull source follower as the buffer stage to drastically extend the bandwidth. The technique of high-frequency common-mode rejection using parasitic capacitor is utilized to guarantee the Opamp stability. In addition, the filter adopts the Q-tuning technique and Opamp GBW compensation mechanism, which relax the GBW requirement of the Opamp to further reduce the power consumption. The filter achieves 1.36 pW/pole/Hz normalized power, 13.1 nVA√Hz input-referred noise density, 15.9 dBm in-band IIP3, and 34 dBm out-of-band IIP3, respectively. The chip is fabricated in a standard 0.18 μm CMOS process, and occupies 0.23 mm2 silicon area without pads.

A 0.47mW 6 th -order 20MHz active filter using highly power-efficient Opamp

This paper presents an ultra-low power 6th-order 7MHz-to−20MHz tunable active-RC low-pass filter. Due to the proposed highly power-efficient Opamp, the filter only consumes 0.47 mA power from 1.8 V supply voltage, corresponding to 3.86 pW/Hz/pole normalized power. The Opamp utilizes an adaptive-biased pole-cancellation push-pull buffer to greatly reduce the power consumption. An adaptive bias circuit is proposed to cooperate with the Opamp to tolerate the PVT variations. The filter achieves 20.9 dBm in-band IIP3, and 298 µVrms integrated input-referred noise. The chip is fabricated in a standard 0.18 µm CMOS process, and occupies 0.21 mm2 silicon area without ESD/pads.

A 4.2 mm

This paper presents a direct-conversion DTV tuner for both VHF and UHF bands. The proposed tuner achieves a noise figure of 2.5-3.5 dB at VHF band and 2-3 dB at UHF band while the LNA consumes only 3.5 mW. An external band-pass LC filter is adopted for RF pre-filtering and providing DC conduction path for noise cancelling balun LNA. The system-level co-design of the LNA and pre-selecting filter further help to obtain 33 dB third-order harmonic rejection ratio without using harmonic rejection mixers. A quantization-noise-compensated fractional- N frequency synthesizer is implemented, achieving 0.5 ° integrated phase error (1 kHz to 4 MHz) at 666 MHz, and suppressing out-of-band ΣΔ noise by 20 dB. The proposed PLL injects compensation current into the loop filter during the PFD delay time, which precisely tracks the VCO output frequency. Highly reconfigurable analog baseband with 0.5-4 MHz bandwidth and 6-54 dB gain is integrated. The tuner is implemented in 65 nm CMOS process, occupies an area of 4.2 mm2, and consumes only 72 mW from a 1.2 V voltage supply.

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This paper presents a CMOS RF tunable 4th-order active bandpass filter with the proposed inductor-less biquads. The NMOS cross-coupled pair is utilized in the biquad for the positive-feedback to form the complex pole, which enables the filter working at high frequency of 5GHz with low power of only 4.8mW from 1.2V power supply. Due to the inductor-less topology, the proposed filter only occupies 0.011mm2 silicon area, which is cost-efficient and suitable for integration on chip. The center frequency can be tuned from 2GHz to 5GHz, and the Q factor is tuned from 2 to 8 to cover different bandwidth from 250MHz to 2.5GHz, which makes it suitable for the multi-band/multi-mode and SDR applications. The filer is demonstrated in a standard 65nm CMOS process. As for the center frequency of 5GHz and Q of 2, the simulated P1dB is -6.7dBm, and the simulated input referred noise (IRN) density is 14.2nV/sqrt(Hz).

72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS

A 1.8V-to-10V high-voltage tolerant level shifter (HVT level shifter) is presented in this paper. This new topology of HVT level shifter makes all the transistors working in safe operating region, and consequently greatly enhances the circuits reliability. It has been fabricated in 0.18 µm CMOS process, and successfully integrated in an embedded EEPROM memory with 10 V programming/erasing voltages in the passive UHF RFID transponders.

Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads

A 17-tap 3.5 Gbps finite impulse response (FIR) pulse shaping filter for 60 GHz transmitters with quadrature phase-shift keying (QPSK) modulation is presented. Measurement results show that an attenuation of 19 dB at 2.2 GHz is achieved with cutoff frequency of 1.76 GHz which enable the 60 GHz transmitter to comply with the stringent spectrum mask requirement. No digital-to-analog converters (DACs) are needed in the proposed approach performed in the analog baseband. The dc power of 3.3 V × 300 mA (55 mA without buffers) is competitive compared to conventional DACs not providing filtering functionality. Implemented in a 0.25 μm SiGe HBT technology, the fully integrated circuit consumes an area of 1.6mm2.

A 1.8V to 10V CMOS level shifter for RFID transponders

A CMOS wideband receiver for BD-Π B2&B3 mode is presented. The chip demonstrates a noise figure of 4.0dB and a 2dB CNR desensitization point of 4dBm at 800MHz GSM blocker. Due to the optimized design of an ESD-protected LNA and a 1/f-noise-reduced high-LO-RF-isolation Mixer, the spurious level is suppressed below −113dBm referred to the RF input. The fractional-N ΣΔ synthesizer obtains LO phase noise of −92dBc/Hz@lKHz and −117dBc/Hz@lMHz, with the reference spurs are below −60dBc. The integrated 4th-order LPF has tunable 7.5MHz/10MHz/15MHz corner frequency. The mixed-signal AGC loop, including 4-bit ADCs, variable gain amplifier and programmable amplifier, achieves 55dB gain dynamic range. The receiver consumes 31mA from a 1.8-V supply voltage while occupying a 5.5-mm2 die area including ESD pads.

A 17-tap 3.5 Gbps finite impulse response pulse shaping filter for 60 GHz transmitter with QPSK modulation

This letter presents a CMOS W-band ×4 frequency multiplier with two cascading push-pull frequency doublers for a W-band frequency synthesizer. A pseudodifferential class-B biased cascode amplifier is adopted for the push-pull frequency doublers to achieve high fundamental rejection and low power consumption. The stacked coplanar spiral transformers are utilized for AC-coupling and single-to-differential transformation. It is fabricated in 65nm CMOS, consumes 16mW from 1.5V power supply, and occupies 0.342mm2. Limited by the frequency range of measurement, the measured output frequency covers from 75 to 110GHz with maximum output power of -14.3dBm at 85.5GHz.