Xincun Ji

A low-power high-speed true single phase clock divide-by-2/3 prescaler

A novel low power high-speed true single-phase clockbased (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18 μm CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10 GHz with 1.836 mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8 GHz with 1.34 mW power consumption.

Reconfigurable chaos in electro-optomechanical system with negative Duffing resonators

Generating various laser sources is important in the communication systems. We propose an approach that uses a mechanical resonator coupled with the optical fibre system to produce periodic and chaotic optical signals. The resonator is structured in such a way that the nonlinear oscillation occurs conveniently. The mechanical apparatus in the configuration is the well known resonating system featured by the negative stiffness. The mechanical resonance is converted to reflected optical signal with the same dynamic properties as the mechanical oscillation, subsequently interacting with the optical signal within the optical fibre. The optical radiative force on the mechanical structure is also considered in the analysis. The coupled electro-optomechanical system has been analysed, and results show that the mechanical resonator has the capability to control the dynamics of the optical signal precisely. The system will have potential applications in tunable laser sources.

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

A resilient tracking circuit for suppressing the timing variation of SRAM sense amplifier enable (SAE) signal is proposed. Pipelined replica bitline technique is used to favour the desired design. Simulation results show that the cycle time is reduced by ∼27% owing to ∼70% reduction of the standard deviation of SAE at a 1.05V supply voltage in 28 nm CMOS technology with four-stage pipeline.

A Linearized Tuning Varactor for Voltage Controlled Oscillator

A linearized tuning varactor for the voltage controlled oscillator (VCO) is proposed in this paper. The capacitance-voltage (C-V) curve is linearized by combining an accumulation MOSFET (AMOS) and PMOS in parallel to form the varactor. Two ring voltage controlled oscillators (ring VCOs) are fabricated and measured with a standard 65-nm CMOS process. They are both identical except for the varactor. The first VCO uses the proposed varactor, and the second one is tuned by a conventional AMOS-only varactor for reference. The ring VCO with the proposed varactor operates from 500.5 to 807.6 MHz, and the VCO gain (KVCO) varies from 183 to 284 MHz/V. Comparing the reference VCO with the AMOS-only varactor, the measured KVCO variability is reduced by 82%. The phase noise is between -89 dBc/Hz and -92 dBc/Hz at 1 MHz offset while dissipating 0.8 mA from a 1.2-V supply.

A 2.4-GHz All-Digital Phase-Locked Loop With a Pipeline-ΔΣ Time-to-Digital Converter

A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. The proposed pipeline-ΔΣ TDC is based on two-stage time quantization with pulse-train time amplifiers. It achieves an SNDR of 80dB and a high resolution up to 0.23ps. A MASH 1-1-1 ΔΣ modulator based on vernier lines is used to achieve third-order noise shaping. The proposed ADPLL has been implemented in a 0.13-μm CMOS technology. The measurement results show a 12-mW total power consumption. The in-band and out-band phase noise are -91dBc/Hz@10kHz and -128dBc/Hz@1MHz, respectively. The RMS jitter and peak-peak jitter are 2.9ps and 21.5ps, respectively.

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter. A TSPC dual-modulus prescaler is proposed to reduce the PLL’s power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops. The measured synthesizer output frequency ranges from 2.16 to 2.7GHz, and consumes 8 mW from a 1.3 V power supply. The in-band phase noise is -98 dBc/Hz at 100 kHz offset, and -115 dBc/Hz at 1 MHz offset at a carrier frequency of 2.438 GHz. The circuit achieves the RMS jitter of 0.86 ps and figure of merit of -230 dB, with the fractional spurs below -55 dBc.

Robust activating timing for SRAM SA with replica cell voltage boosted circuit

A boosted replica cell voltage control scheme has been proposed for reducing the process-variation of SRAM sense amplifier. This technique suppresses the timing variation by boosting the replica cell voltage. Simulation result shows that the variation of the generated timing was 34.6% smaller when compared with conventional technique, and the cycle time is reduced by 17% at a 0.85V VDD operation in TSMC 65 nm technology with this scheme.