Xu Xiao-Bo

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium (SiGe) heterojunction bipolar transistor (HBT) on thin silicon-on-insulator (SOI) has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base—collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiGe devices and circuits.

An Analytical Avalanche Multiplication Model for Partially Depleted Silicon-on-Insulator SiGe Heterojunction Bipolar Transistors

An analytical expression for avalanche multiplication of a novel vertical SiGe partially depleted heterojunction bipolar transistor (HBT) on a thin silicon-on-insulator (SOI) layer is obtained, considering vertical and horizontal impact ionization effects. The avalanche multiplication is found to be dependent on the collector width and doping concentration, and shows kinks with the increase of reverse base-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the experimental and simulation data and is found to be significant for the design and simulation of 0.13 μm millimeter wave SiGe SOI BiCMOS technology.

Analytical base-collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

The base—collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors (HBTs) on silicon on insulator (SOI) is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector—base bias—and shows a kink as the reverse collector—base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.

The study of parallel strain distribution in channel of PMOSFET with silicon-germanium source and drain regions

The finite-element model of strained silicon PMOSFET was established based on the structure of small uniaxial strained silicon device. Using thermal strain method to simulate the parallel strain distribution of the channel through ANSYS simulation platform. The results present that: (1)the compressive strain on the channel surface is quite uniform along the direction parallel to the channel, the compressive strain in the center of channel decreases with the increasing distance from the channel surface, which transforms into tensile strain when the distance reaches or beyonds the etching depth of silicon-germanium source and drain. (2)the strain in the channel will correspondingly increase with the decreasing channel length or increasing etching depth of silicon-germanium source and drain or increasing germanium fraction of source and drain. The conclusion provides a design basis to improve the device performance by controlling the strain, in addition, the conclusion is in line with the relevant literature.

Study of threshold voltage modeling for small-scaled strained Si nMOSFET

In this paper, based on the distribution of electric field in the channel which follows the Guass Law, an analytical expression of Quasi-2D threshold voltage model for strained Si nMOSFET with Polycrystalline SiGe gate was established. With this model, the variation threshold voltage with its design physical and geometric parameters can be predicted, such as Ge content, oxide thickness, doping concentration, gate length, and drain bias. The validity of the model was proved by ISE TCAD simulation. This model is significant for the design of high performance strained Si nMOSFET

Impact of [110]/(001) uniaxial stress on valence band structure and hole effective mass of silicon

The valence band structure and hole effective mass of silicon under a uniaxial stress in (001) surface along the [110] direction were detailedly investigated in the framework of the k p theory. The results demonstrated that the splitting energy between the top band and the second band for uniaxial compressive stress is bigger than that of the tensile one at the same stress magnitude, and of all common used crystallographic direction, such as [110], [001], [10] and [100], the effective mass for the top band along [110] crystallographic direction is lower under uniaxial compressive stress compared with other stresses and crystallographic directions configurations. In view of suppressing the scattering and reducing the effective mass, the [110] crystallographic direction is most favorable to be used as transport direction of the charge carrier to enhancement mobility when a uniaxial compressive stress along [110] direction is applied. The obtained results can provide a theory reference for the design and the selective of optimum stress and crystallorgraphic direction configuration of uniaxial strained silicon devices.

Weak avalanche multiplication in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

In this paper, we propose an analytical avalanche multiplication model for the next generation of SiGe siliconon-insulator (SOI) heterojunction bipolar transistors (HBTs) and consider their vertical and lateral impact ionizations for the first time. Supported by experimental data, the analytical model predicts that the avalanche multiplication governed by impact ionization shows kinks and the impact ionization effect is small compared with that of the bulk HBT, resulting in a larger base-collector breakdown voltage. The model presented in the paper is significant and has useful applications in the design and simulation of the next generation of SiGe SOI BiCMOS technology.

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the collector resistance of a novel vertical SiGe heterojunction bipolar transistor (HBT) on thin film silicon-on-insulator (SOI) is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate—collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μm millimeter-wave SiGe SOI BiCMOS devices.