Xue-Feng Zheng

Breakdown voltage and current collapse of F-plasma treated AlGaN/GaN HEMTs

The breakdown and the current collapse characteristics of high electron mobility transistors (HEMTs) with a low power F-plasma treatment process are investigated. With the increase of F-plasma treatment time, the saturation current decreases, and the threshold voltage shifts to the positive slightly. Through analysis of the Schottky characteristics of the devices with different F-plasma treatment times, it was found that an optimal F-plasma treatment time of 120 s obviously reduced the gate reverse leakage current and improved the breakdown voltage of the devices, but longer F-plasma treatment time than 120 s did not reduce gate reverse leakage current due to plasma damage. The current collapse characteristics of the HEMTs with F-plasma treatment were evaluated by dual pulse measurement at different bias voltages and no obvious deterioration of current collapse were found after low power F-plasma treatment.

Investigation of trap states under Schottky contact in GaN/AlGaN/AlN/GaN high electron mobility transistors

Forward gate-bias stress experiments are performed to investigate the variation of trap states under Schottky contact in GaN-based high electron mobility transistors. Traps with activation energy ET ranging from 0.22 eV to 0.31 eV are detected at the gate-semiconductor interface by dynamic conductance technique. Trap density decreases prominently after stressing, particularly for traps with ET > 0.24 eV. X-ray photoelectron spectroscopy measurements reveal a weaker Ga-O peak on the stressed semiconductor surface. It is postulated that oxygen is stripped by Ni to form NiO upon electrical stress, contributing to the decrease in ON donor sates under the gate contact.

Observation of threshold voltage instabilities in AlGaN/GaN MIS HEMTs

We report the investigation of threshold voltage (V th) instability of AlGaN/GaN metal–insulator–semiconductor (MIS) HEMTs with SiN gate dielectric under forward gate bias stress. A systematic step stress-recovery experiment is implemented to study the charging and discharging kinetics of pre-existing defects. A two-step trapping process is identified: electron fast trapping into SiN/ GaN interface by tunneling through the thin GaN/AlGaN layer followed by the slow dynamics featuring a logarithmic time-dependence of the V th shift. Full and fast recovery of the V th instability is induced when devices are subjected to a large negative gate bias, while a slow and incomplete detrapping process occurs at V g = 0 V. In addition, pulsed current–voltage measurements are developed to estimate trap densities and monitor defect generation before and after stressing.

Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors under reverse-bias stress

Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors are investigated. The gate leakage current decreases significantly upon removing the SiN layer and no clear critical voltage for the sudden degradation of the gate leakage current can be observed in the reverse-bias step-stress experiments. Gate-lag measurements reveal the decrease of the fast-state surface traps and the increase of slow-state traps after the passivation layer removal. It is postulated that consistent surface charging relieves the electric field peak on the gate edge, thus the inverse piezoelectric effect is shielded.

Improvement of the off-state breakdown voltage with field plate and low-density drain in AlGaN/GaN high-electron mobility transistors

We present an AlGaN/GaN high-electron mobility transistor (HEMT) device with both field plate (FP) and low-density drain (LDD). The LDD is realized by the injection of negatively charged fluorine (F–) ions under low power in the space between the gate and the drain electrodes. With a small-size FP and a LDD length equal to only 31% of the gate-drain spacing, the device effectively modifies the electric field distribution and achieves a breakdown voltage enhancement up to two times when compared with a device with only FP.

Interaction between hot carrier aging and PBTI degradation in nMOSFETs: Characterization, modelling and lifetime prediction

Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design. Previous works were mainly based on separate HCA and PBTI instead of Interacted HCA-PBTI Degradation (IHPD). The key advance of this work is to develop a methodology that enables accurate modelling of IHPD through understanding the charging/discharging and generation kinetics of different types of defects during the interaction between HCA and PBTI. It is found that degradation during alternating HCA and PBTI stress cannot be modelled by independent HCI/PBTI. Different stress sequence, i.e. HCA-PBTI-HCA and PBTI-HCA-PBTI, lead to completely different degradation kinetics. Based on the Cyclic Anti-neutralization Model (CAM), for the first time, IHPD has been accurately modelled for both short and long channel devices. Complex degradation mechanisms and kinetics can be well explained by our model. Our results show that device lifetime can be underestimated by one decade without considering interaction.

The Transport Mechanisms of Reverse Leakage Current in Ultraviolet Light-Emitting Diodes

The transport mechanisms of the reverse leakage current in the UV light-emitting diodes (380 nm) are investigated by the temperature-dependent current-voltage measurement first. Three possible transport mechanisms, the space-limited-charge conduction, the variable-range hopping and the Poole—Frenkel emission, are proposed to explain the transport process of the reverse leakage current above 295 K, respectively. With the in-depth investigation, the former two transport mechanisms are excluded. It is found that the experimental data agree well with the Poole—Frenkel emission model. Furthermore, the activation energies of the traps that cause the reverse leakage current are extracted, which are 0.05 eV, 0.09 eV, and 0.11 eV, respectively. This indicates that at least three types of trap states are located below the bottom of the conduction band in the depletion region of the UV LEDs.

Reverse blocking characteristics and mechanisms in Schottky-drain AlGaN/GaN HEMT with a drain field plate and floating field plates*

In this paper, a novel AlGaN/GaN HEMT with a Schottky drain and a compound field plate (SD-CFP HEMT) is presented for the purpose of better reverse blocking capability. The compound field plate (CFP) consists of a drain field plate (DFP) and several floating field plates (FFPs). The physical mechanisms of the CFP to improve the reverse breakdown voltage and to modulate the distributions of channel electric field and potential are investigated by two-dimensional numerical simulations with Silvaco-ATLAS. Compared with the HEMT with a Schottky drain (SD HEMT) and the HEMT with a Schottky drain and a DFP (SD-FP HEMT), the superiorities of SD-CFP HEMT lie in the continuous improvement of the reverse breakdown voltage by increasing the number of FFPs and in the same fabrication procedure as the SD-FP HEMT. Two useful optimization laws for the SD-CFP HEMTs are found and extracted from simulation results. The relationship between the number of the FFPs and the reverse breakdown voltage as well as the FP efficiency in SD-CFP HEMTs are discussed. The results in this paper demonstrate a great potential of CFP for enhancing the reverse blocking ability in AlGaN/GaN HEMT and may be of great value and significance in the design and actual manufacture of SD-CFP HEMTs.

Characteristics and threshold voltage model of GaN-based FinFET with recessed gate

In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established, which agrees with both the experimental results and simulation results.

Low specific on-resistance GaN-based vertical heterostructure field effect transistors with nonuniform doping superjunctions*

A novel GaN-based vertical heterostructure field effect transistor (HFET) with nonuniform doping superjunctions (non-SJ HFET) is proposed and studied by Silvaco-ATLAS, for minimizing the specific on-resistance (R on A) at no expense of breakdown voltage (BV). The feature of non-SJ HFET lies in the nonuniform doping concentration from top to bottom in the n- and p-pillars, which is different from that of the conventional GaN-based vertical HFET with uniform doping superjunctions (un-SJ HFET). A physically intrinsic mechanism for the nonuniform doping superjunction (non-SJ) to further reduce R on A at no expense of BV is investigated and revealed in detail. The design, related to the structure parameters of non-SJ, is optimized to minimize the R on A on the basis of the same BV as that of un-SJ HFET. Optimized simulation results show that the reduction in R on A depends on the doping concentrations and thickness values of the light and heavy doping parts in non-SJ. The maximum reduction of more than 51% in R on A could be achieved with a BV of 1890 V. These results could demonstrate the superiority of non-SJ HFET in minimizing R on A and provide a useful reference for further developing the GaN-based vertical HFETs.