Yue Hao

Physical properties and electrical characteristics of H2O-based and O3-based HfO2 films deposited by ALD

Ozone (O3) and H2O are used as the oxidant to deposit hafnium oxide (HfO2) thin films on p-type Si (1 0 0) wafers by atomic layer deposition (ALD). The physical properties and electrical characteristics of HfO2 films change greatly for different oxidants and deposition temperature. Compared with O3 as the oxidant, HfO2 films grown with H2O as the oxidant are more consistent in composition and growth rate. The O3based HfO2 films have lower C impurity and higher concentration N impurity than the H2O-based HfO2 films. The impact of the annealing process on the electrical properties and stability of HfO2 films are also investigated. A width step is observed in the O3-based HfO2 C–V curves, which disappears after annealing process. It is because the unstable Hf–O–N and Hf–N bonds in O3-based HfO2 films are re-bonded with the non-HfO2 oxygen after annealing process, and the binding energy of N1s shifts.

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

Abstract In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.

Degradation model of the electron gate current in PMOSFET

In this paper, we present an accurate degradation model of the electron gate current in PMOSFETs. The analytical and physics-based model was developed considering trapped-electron effect on the gate current during the stress. This model can be used to extract exactly the trapped electron density in the gate oxide of PMOSFET and to model the hot-carrier lifetime of the devices.

An improved electron mobility model for wurtzite ZnO

An improved analyticl model for the electron mobility in wurtzite ZnO is developed. The numerical results of Monte Carlo transport simulations in previous literature have been evaluated and referred as the basis for the model development. The improved model describes properly the variation of the field-dependent mobility with carrier concentration and temperature, not only for room temperature but also for temperatures considerably higher than 300K, showing good agreements with previous results.

Performance analysis of dual-material gate SOI MOSFET

In this paper, a novel device structure called dual-material gate SOI MOSFET (DMG SOI MOSFET) is proposed to restrain drain-induced barrier lowering (DIBL) and short-channel effect (SCE) for the advanced nanometer process. The analytical threshold voltage model of novel structure device is presented, and the electrical characteristics are analyzed. The DMG SOI MOSFET with high k dielectric shows better performance in suppressing DIBL and enhancing carrier transport efficiency than the conventional SOI MOSFET. The DIBL is reduced with increasing dielectric constant. The analytical threshold voltage model is in good agreement with the two-dimensional device simulator ISE.

Investigation of electrical characteristics of NdAlO 3 /SiO 2 stack gate

Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission and Schottky emission are the main transport mechanisms of the gate leakage current for the fresh sample, while F-N tunneling and Schottky emission are responsible for the gate leakage current after stress.

A comprehensive transport model for the electron mobility in Al x Ga 1−x N lattices-matched to GaN

A comprehensive model for the electron mobility in AlGaN lattices-matched to GaN is developed. A large number of experimental and theoretical mobility data and the results of Monte Carlo transport simulations in previous literature have been evaluated and referred as the basis for the model development. The proposed model describes the variation of the field-dependent mobility with carrier concentration, temperature, Al composition, random alloy, etc., showing good agreements with previous results. More emphases have been put on the effects of the temperature and random alloy in this work.

Study on the degradation induced by donor interface state in deep-sub-micron grooved-gate P-channel MOSFET’s

Abstract The degradation of electrical performance induced by interface states is one main reason for failure occurs in deep-sub-micron MOS devices. Especially for grooved-gate MOS devices, there are a large amount of interface states and flaw formed during the etching of concave. Based on the hydrodynamics energy transport model, using MEDICI simulator, the degradation induced by donor interface states is analyzed for deep-sub-micron grooved-gate PMOSFET’s with different channel doping densities and compared with that of corresponding conventional planar PMOSFET’s. The results also compared with that of degradation induced by acceptor interface states. The simulation results indicate that the degradation induced by same interface state density in grooved-gate PMOSFET’s is larger than that in planar PMOSFET’s, and in both structure devices, the impact of electron donor interface states on device performance is far larger than that of hole donor interface state. This work gives an useful insight of mechanism of hot-carrier degradation for grooved gate MOS devices and lays a solid foundation for grooved gate devices used in deep-sub-micron region VLSI practically.