Xuehao Mou

Effects of Electrode Layer Band Structure on the Performance of Multilayer Graphene-hBN-Graphene Interlayer Tunnel Field Effect Transistors

Interlayer tunnel field-effect transistors based on graphene and hexagonal boron nitride (hBN) have recently attracted much interest for their potential as beyond-CMOS devices. Using a recently developed method for fabricating rotationally aligned two-dimensional heterostructures, we show experimental results for devices with varying thicknesses and stacking order of the graphene electrode layers and also model the current-voltage behavior. We show that an increase in the graphene layer thickness results in narrower resonance. However, due to a simultaneous increase in the number of sub-bands and decrease of sub-band separation with an increase in thickness, the negative differential resistance peaks becomes less prominent and do not appear for certain conditions at room temperature. Also, we show that due to the unique band structure of odd number of layer Bernal-stacked graphene, the number of closely spaced resonance conditions increase, causing interference between neighboring resonance peaks. Although this can be avoided with even number of layer graphene, we find that in this case the bandgap opening present at high biases tend to broaden the resonance peaks.

Quantum transport simulations on the feasibility of the bilayer pseudospin field effect transistor (BiSFET)

The feasibility of ultra low-voltage switching in the proposed Bilayer PseudoSpin Field-Effect Transistor (BiSFET) “beyond CMOS” device concept is illustrated using quantum transport simulations. The BiSFET relies on possible room-temperature superfluid condensation in dielectrically separated graphene layers. Simulations illustrate resulting greatly enhanced interlayer tunneling, and critical voltages for switching between ON and OFF interlayer conductance states below the thermal voltage of ~26 mV at 300 K. The BiSFET switching mechanism is also contrasted to the “drag-counterflow” biasing configuration with much higher switching voltages.

Quantum transport simulation of Bilayer pseudoSpin Field-Effect Transistor (BiSFET) with tight-binding hartree-fock model

A simulation tool for modeling superfluid quantum transport in the proposed Bilayer Psuedo-spin Field Effect Transistor (BiSFET) and related systems is described and demonstrated. An interlayer Fock exchange interaction is incorporated into a π-orbital based atomistic tight-binding model of transport in two graphene layers separated by a tunnel barrier. Simulation results support and extend expectations based on bulk analysis such as superfluid condensate formation, enhanced interlayer tunneling and the sub-thermal voltage (sub-kBT/q) switching. Extension of this method to other quasi-two dimensional material systems should be possible as well.

Full-band simulations of single-particle resonant tunneling in transition metal dichalcogenide-based interlayer tunneling field-effect transistors

We model and simulate the resonant tunneling and I-V characteristics of Interlayer Tunneling Field-Effect Transistors (ITFETs) based on transition metal dichalcogenide monolayers, MoS2 layers here, using quantum transport simulations with a full-band model. Gate-controllable resonant peaks are demonstrated and the short channel effects on resonance broadening are studied.

Quantum transport simulation of exciton condensate transport physics in a double-layer graphene system

Spatially indirect electron-hole exciton condensates stabilized by interlayer Fock exchange interactions have been predicted in systems containing a pair of two-dimensional semiconductor or semimetal layers separated by a thin tunnel dielectric. The layer degree of freedom in these systems can be described as a pseudospin. Condensation is then analogous to ferromagnetism, and the interplay between collective and quasiparticle contributions to transport is analogous to phenomena that are heavily studied in spintronics. These phenomena are the basis for pseudospintronic device proposals based on possible low-voltage switching between high (nearly shorted) and low interlayer conductance states and on near perfect Coulomb drag-counterflow current along the layers. In this work, a quantum transport simulator incorporating a non-local Fock exchange interaction is presented, and used to model the essential transport physics in the bilayer graphene system. Finite size effects, Coulomb drag-counterflow current, critical interlayer currents beyond which interlayer DC conductance collapses at sub-thermal voltages, non-local coupling between interlayer critical currents in multiple lead devices, and an Andreev-like reflection process are illustrated.

Interplay among Bilayer pseudoSpin field-effect transistor (BiSFET) performance, BiSFET scaling and condensate strength

It has been proposed that superfluid excitonic condensates may be possible in dielectrically separated graphene layers or other two-dimensional materials. This possibility was the basis for the proposed ultra-low power Bilayer pseudoSpin Field-effect Transistor (BiSFET). Previously, we developed an atomistic tight-binding quantum transport simulator, including the non-local exchange interaction, and used it to demonstrate the essential excitonic superfluid transport physics which underlies the proposed BiSFET in presence of such a condensate. Here we report on extension of that work to analyze dependencies on device scaling and the condensate strength of BiSFET performance and required device parameters including interlayer conductance, and critical current and voltage.

Gate tunable resonant tunneling in graphene-based heterostructures and device applications

Electron tunneling is receiving increased emphasis as the physical mechanism of operation in emerging devices that seek to mitigate power dissipation issues in aggressively scaled CMOS technology. A tunneling field-effect transistors (TFET) consisting of a gated p-i-n junction is arguably the best known example. In a separate class of tunneling devices, consisting of two semiconducting layers separated by a barrier, the inter-layer tunneling current-voltage characteristics possess gate-tunable negative differential resistance [1]-[3], which is subsequently used to implement Boolean logic functions [4]. We describe here the fabrication, characterization, and benchmarking of inter-layer TFETs (ITFETs) using double bilayer graphene heterostructures separated by hexagonal boron-nitride dielectric as example [Fig. 1(a)].

Bilayer Pseudospin Junction Transistor (BiSJT) for “Beyond-CMOS” Logic

A novel beyond-CMOS device concept, the Bilayer pseudoSpin Junction Transistor (BiSJT), is proposed. Like the previously proposed Bilayer pseudoSpin FET (BiSFET), the BiSJT is motivated by the possibility of interlayer electron–hole exciton condensation in bilayer 2-D material systems, and could provide switching energies of a few 10 s of zJ, orders of magnitude below even end-of-the-roadmap CMOS. The BiSJT is, however, current-controlled, and may allow for simpler device design, smaller device area, and more flexible gate design.

Theoretical study of the spontaneous electron-hole exciton condensates between n and p-type MoS 2 monolayers, toward beyond CMOS applications

We model equilibrium properties of possible room-temperature electron-hole exciton condensates formed between two dielectrically separated transition metal dichalcogenide (TMD) layers, MoS2 layers here, toward application to novel beyond CMOS devices. Our simulation method employs an interlayer Fock exchange interaction incorporated into an otherwise intra-layer tight-binding Hamiltonian within a maximally-localized Wannier function (MLWF) basis set.

Ultralow-Power Pseudospintronic Devices via Exciton Condensation in Coupled Two-Dimensional Material Systems

“Pseudospintronic” device concepts, novel “beyond-CMOS” device proposals targeted toward revolutionizing the current semiconductor technology based on MOSFETs and CMOS logic, are addressed in detail. These pseudospin devices include the voltage-controlled Bilayer pseudoSpin Field-Effect Transistor (BiSFET) and the current-controlled Bilayer pseudoSpin Junction Transistor (BiSJT). MOSFETs are confronted by the intractable physics of thermionic emission and resulting source-to-drain leakage that limits voltage scaling. As a result, CMOS faces an “energy crisis” much as the one faced by bipolar junction transistor-based logic that led to CMOS. As for many other beyond-CMOS concepts, these pseudospintronic devices are based on a completely different physics of switching, potentially allowing much lower voltage and power operation. These pseudospintronic device concepts employ possible room-temperature interlayer electron–hole exciton condensates between two dielectrically separated layers of two-dimensional (2D) materials for subthermal voltage (sub-k B T/q) switching, specifically from a nearly shorted interlayer conductance state to a highly resistive interlayer conductance state with increasing interlayer voltage. These collective exciton states with their “which-layer” degree of freedom are somewhat analogous to collective spin states in magnets, which is the origin of the “pseudospintronics” moniker. Device performance in the presence of such condensates is the primary focus of this work; the possibility of room-temperature condensates, itself, is addressed by other research still in progress. We begin with a discussion of the underlying physics. Graphene-based pseudospintronic systems then are analyzed using quantum transport simulations incorporating the nonlocal exchange interaction. However, the essential transport physics should be much the same for other 2D material systems, including transition metal dichalcogenides for which the realization of the condensate may be easier. The BiSFET and BiSJT device concepts are presented in detail, and basic logic gate designs are illustrated for each. Compact device models are developed and SPICE-level circuit simulations are performed to demonstrate possible switching energies on the scale of or below a tenth of an attojoule, well below even end-of-the-road-map CMOS. However, like many other beyond-CMOS concepts, these devices remain concepts without solid experimental embodiments. The fabrication concerns of such novel devices are also discussed along with recent experimental progress.