Xuehong Yu

A Technology Overview of the PowerChip Development Program

The PowerChip research program is developing technologies to radically improve the size, integration, and performance of power electronics operating at up to grid-scale voltages (e.g., up to 200V) and low-to-moderate power levels (e.g., up to 50W) and demonstrating the technologies in a high-efficiency light-emitting diode driver, as an example application. This paper presents an overview of the program and of the progress toward meeting the program goals. Key program aspects and progress in advanced nitride power devices and device reliability, integrated high-frequency magnetics and magnetic materials, and high-frequency converter architectures are summarized.

Microfabrication of air core power inductors with metal-encapsulated polymer vias

This paper reports three-dimensional (3-D) microfabricated toroidal inductors intended for power electronics applications. A key fabrication advance is the exploitation of thick metal encapsulation of polymer pillars to form a vertical via interconnections. The radial conductors of the toroidal inductor are formed by conventional plating-through-mold techniques, while the vertical windings (up to 650 µm in height) are formed by polymer cores with metal plated on their external surfaces. This encapsulated polymer approach not only significantly reduces the required plating time but also exploits the relative ease of fabricating high-aspect-ratio SU-8 pillars. To form the top radial conductors, non-photopatternable SU-8 is introduced as a thick sacrificial layer. Two toroidal inductor geometries were fabricated and tested. The first inductor had an inner diameter of 2 mm, an outer diameter of 6 mm, 25 turns and a vertical via height of 650 µm. The second inductor had an inner diameter of 4 mm, an outer diameter of 8 mm, 50 turns and a vertical via height of 650 µm. Both inductor geometries were successfully fabricated and characterized in the frequency range of 0.1−100 MHz. Characterization results of the 25- and 50-turn inductors showed an average inductance of 76 and 200 nH, a low frequency (0.1 MHz) resistance of 0.2 and 1 Ω and a quality factor of 35 and 24 at 100 MHz, respectively. Finite-element simulations of the inductors were performed and agreed with the measured results to within 8%. The turn-to-turn breakdown voltage was measured to be in excess of 800 V and currents as high as 0.5 A could be successfully carried by the inductor windings.

Silicon-embedded 3D toroidal air-core inductor with through-wafer interconnect for on-chip integration

This paper presents a CMOS-compatible process for fabrication of 3D structures embedded in the volume of a silicon wafer, and capable of interconnection to circuitry on the wafer surface. The key challenge of embedding structures in the silicon substrate is processing inside deep silicon trenches. This difficulty is overcome by means of several key techniques: multilevel wafer etching; cavity shaping; fine proximity lithography at the bottom of trenches; and laminated dry-film lithography on complex 3D structures. As a technology demonstration, a topologically complex 3D toroidal inductor is fabricated in a deep silicon trench, and is coupled to the wafer surface with high-power, electroplated through-wafer interconnect. Inductors fabricated in these trenches achieved an overall inductance of 60 nH, dc resistance of 399 MΩ, and quality factor of 17.5 at 70 MHz.

Silicon-Embedding Approaches to 3-D Toroidal Inductor Fabrication

This paper presents complementary-metal-oxide-semiconductor-compatible silicon-embedding techniques for on-chip integration of microelectromechanical-system devices with 3-D complex structures. By taking advantage of the “dead volume” within the bulk of the silicon wafer, functional devices with large profile can be embedded into the substrate without consuming valuable die area on the wafer surface or increasing the packaging complexity. Furthermore, through-wafer interconnects can be implemented to connect the device to the circuitry on the wafer surface. The key challenge of embedding structures within the wafer volume is processing inside deep trenches. To achieve this goal in an area-efficient manner, straight-sidewall trenches are desired, adding additional difficulty to the embedding process. Two approaches to achieve this goal are presented in this paper, i.e., a lithography-based process and a shadow-mask-based process. The lithography-based process utilizes a spray-coating technique and proximity lithography in combination with thick epoxy processing and laminated dry-film lithography. The shadow-mask-based process employs a specially designed 3-D silicon shadow mask to enable simultaneous metal patterning on both the vertical sidewall and the bottom surface of the trench during deposition, eliminating multiple lithography steps and reducing the process time. Both techniques have been demonstrated through the embedding of the topologically complex 3-D toroidal inductors into the silicon substrate for power supply on-chip (PwrSoC) applications. Embedded 3-D inductors that possess 25 turns and a diameter of 6 mm in a silicon trench of 300-μm depth achieve overall inductances of 45-60 nH, dc resistances of 290-400 mΩ, and quality factors of 16-17.5 at 40-70 MHz.

Modeling and measured verification of stored energy and loss in MEMS toroidal inductors

This paper presents the derivation and verification of a sinusoidal steady-state equivalent-circuit model for microfabricated inductors developed for use in integrated power electronics. These inductors have a low profile, a toroidal air core, and a single-layer winding fabricated via high-aspect-ratio molding and electroplating. Such inductors inevitably have a significant gap between winding turns. This makes the equivalent resistance more difficult to model. The low profile increases the significance of the energy that is stored in the winding, which together with the winding gap makes the equivalent inductance more difficult to model. The models presented here account for these effects. Finally, the models are verified against results from 2-D and 3-D finite-element analysis (2-D FEA and 3-D FEA) direct measurement, and from in-circuit experimentation. In all cases, the equivalent-circuit model is observed to be accurate to within several percentage.

Silicon-embedded toroidal inductors with magnetic cores: Design methodology and experimental validation

An approach to the ultimate integration and miniaturization of MEMS-based 3-D magnetic components involves embedding the volume of the magnetic structures within the volume of the silicon wafer itself, exploiting microfabricated windings to create current paths, and utilizing embedded magnetic cores within the limited footprint of these components to boost the magnetic performance. However, this embedding approach imposes volumetric and microfabrication constraints that require an unusual magnetic component optimization methodology compared to wire-wound inductors and PCB inductors. These constraints dictate embedded toroidal inductors with non-overlapping windings and thin magnetic cores, and impose additional limitations on inductor design parameters such as pattern resolution, the number of winding turns and winding thickness; these constraints complicate the trade-offs to be made in designing core-integrated inductors. A design methodology encompassing these constraints is therefore needed. For a targeted inductance value within a given footprint, our design methodology addresses an inductor with a maximized quality factor based on the trade-offs between copper loss and core loss. To illustrate this methodology, silicon-embedded inductors with iron powder cores are designed and fabricated; a quality factor of 24 is achieved at 30 MHz.

Watt-level wireless power transfer based on stacked flex circuit technology

This paper presents the design, simulation, fabrication, and experimental characterization of a multi-layer spiral inductor that acts as the receiver coil for watt-level wireless power transfer. The inductor was designed with multiple vertical laminations where 88-μm-thick copper coils were separated by 25-μm-thick Kapton films using a flexible PCB fabrication technique. This Cu-Kapton approach has the potential for lower-cost coil fabrication than relatively expensive Litz-wire winding techniques. Varying turn widths were implemented to account for proximity effects and maximize the coil current distribution uniformity inside the coil windings at a given frequency, as validated by two-dimensional electromagnetic simulations. The multi-layer design incorporating lamination of four layers together with width variation exhibited a Q-factor improvement of 150% in comparison to the single-layer inductor. It was measured to have an inductance of 17 μH and a Q-factor of 50 at 300 kHz with an outer diameter of 5 cm. With a Litz-wire inductor as the transmitter coil for wireless power transfer, a load power of 7 Watts was transferred at 300 kHz over a distance of 5 cm and 5 Watts over 10 cm, two times the coil diameter, achieving an overall efficiency (defined as the ratio of the received load power to the total input power to the driving circuitry) of 46% and 23% respectively. In comparison, a manually-wound Litz-wire receiver coil with same characteristics under similar conditions demonstrated an overall efficiency of 58% and 39% at one and two-diameter distances, respectively.

Fabrication of multi-layer windings in silicon-embedded toroidal inductors

We report a fabrication method for silicon-embedded toroidal inductors with multi-layer windings, based on 3D shadow mask technology. Such multilayer devices boost inductance density within a limited footprint, which is vital for realization of integrated high-power high-frequency power converters. Fabrication of embedded toroidal inductors with double-layer windings is illustrated; characterization shows a 4x inductance increase compared to an embedded inductor with single-layer windings.