Xuelong Zhang

High accuracy digital aging monitor based on PLL-VCO circuit

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

Highly stable data SRAM-PUF in 65nm CMOS process

Physical Unclonable Functions (PUF) are innovative circuit extract key relying upon the intrinsic process variations in interconnects and transistors of integrated circuits. It can be used in many modern cryptographic protocols as keys or unique digital ID. This paper proposes a highly stable SRAM-PUF cell with isolate nMOS to improve the robustness of the circuit. This design is implemented in SMIC 65nm LP CMOS technology and the layout area of the cell occupies 1.9μm×1.15μm. The simulation results show that the SNM of the proposed solution improve 45% performance during a read operation compared with a traditional SRMA-PUF cell architecture. Meanwhile, it has a high level of stability under different corners.

A PUFs-based hardware authentication BLAKE algorithm in 65 nm CMOS

ABSTRACT This paper presents a hardware authentication BLAKE algorithm based on physical unclonable functions (PUFs) in Taiwan Semiconductor Manufacturing Company low-power 65 nm CMOS. To support hardware authentication feature, PUFs have been organised in BLAKE algorithm as the salt value. The trials table method is used to improve the robust of PUFs, resulting in approximately 100% stability against supply voltage variations form 0.7 V to 1.6 V. By discussing the G-function of BLAKE algorithm, the hardware implementation is considered for acceleration, resulting in significant performance improvements. The die occupies 2.62 mm2 and operates maximum frequency 1.0 GHz at 1.6 V. Measured results show that PUFs have great random characteristic and the authentication chip dissipates an average power of 91 mW under typical condition at 1.2 V and 780 MHz. In comparison with other works, the PUFs-based BLAKE algorithm has hardware authentication feature and improves throughput about 45%.