Yuejun Zhang

Model and physical implementation of multi-port PUF in 65 nm CMOS

In modern cryptographic systems, multi-port physically unclonable function (MPUF) is an efficient mechanism for many security applications, which extracts secret information inherently embedded in the unclonable physical variations and generates multiple secret keys. In this article, we propose an explicit analytic MPUF model, which is useful in predicting the effect of parameter changes on the state as well as in optimizing the design of PUF. Then, a novel MPUF based on register file is designed and fabricated in TSMC low-power 65 nm CMOS technology. There are four ports in the MPUF, and each port produces a 256-bit key. The chip has an area of 0.045 mm2, and has a peak clock frequency of 1.25 GHz at 1.2 V. The average power consumption is 13.8 mW at 27°C. Being multi-ports technology and high operation frequency, the throughput of MPUF improves about 50 times compared to the other works. We carry out a robust test by varying the operational conditions such as supply voltage, temperature and noise. The measured results show that the reliability achieves 98.1% at worse case and has a certain improvement compared with the proposed works. The reliability operates at an acceptable range in integrated circuit identification (ICID).

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing

A novel area-efficient dual replica-bitline delay technique is proposed in this brief to improve process-variation-tolerance of low voltage SRAM application. This strategy suppresses the timing variation by adding one another replica-bitline and introducing novel replica cell which has the same size as conventional. Simulation results in TSMC 65 nm LP technology show that more than 32.3% timing variation is reduced and 18% cycle time is saved at low supply voltage without any area overhead.

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

This paper details the design of a 64 × 32 bit 4-read 2write register file in TSMC 65 nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65 nm LP technology. The measured results demonstrate operation of 0.77 GHz, consuming 7.08 mW at 1.2 V, and occupying 0.018 mm2.

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process

This brief proposes an ultralow-voltage four-read-port and two-write-port multiported register file with a novel architecture of read word-line sharing strategy for energy/area efficiency. Static read circuits and memory cells with nonminimum channel length are introduced to improve the ultralow-voltage performance. The chip of this register file is fabricated in 65-nm LP CMOS process and occupies the area of 0.019 mm

A PUFs-based hardware authentication BLAKE algorithm in 65 nm CMOS

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Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS

. Test results show that the minimum operation voltage is 320 mV with its corresponding max frequency 110 KHz. The minimum energy consumption is 0.94 pJ/cycle at the point of 400 mV, 850 KHz, corresponding to 0.15 fJ/port/bit/cycle after normalization. Compared with the state-of-the-art designs, it improves energy efficiency by 25% and saves the area by 58.7%.

Multiport register file memory cell and placement and routing method thereof

ABSTRACT This paper presents a hardware authentication BLAKE algorithm based on physical unclonable functions (PUFs) in Taiwan Semiconductor Manufacturing Company low-power 65 nm CMOS. To support hardware authentication feature, PUFs have been organised in BLAKE algorithm as the salt value. The trials table method is used to improve the robust of PUFs, resulting in approximately 100% stability against supply voltage variations form 0.7 V to 1.6 V. By discussing the G-function of BLAKE algorithm, the hardware implementation is considered for acceleration, resulting in significant performance improvements. The die occupies 2.62 mm2 and operates maximum frequency 1.0 GHz at 1.6 V. Measured results show that PUFs have great random characteristic and the authentication chip dissipates an average power of 91 mW under typical condition at 1.2 V and 780 MHz. In comparison with other works, the PUFs-based BLAKE algorithm has hardware authentication feature and improves throughput about 45%.