Y.-C. Huang

Re-investigation of gate oxide breakdown on logic circuit reliability

Gate oxide breakdown has been studied in the circuit-like patterns, i.e. e-Fuse arrays and two-stage inverter circuit. It is observed that time-dependent dielectric breakdown (TDDB) lifetime of eFuse chip is larger compared to discrete devices. Gate oxide breakdown study using two-stage inverter circuit (1st-stage I/O N/PMOS worked as current limiting transistors and 2nd-stage core N/PMOS is stressed transistors) reveals that, even by applying a significant high voltage stress (≤ 3×Vdd) on stressed device, the stress device will suffer only soft breakdown not a hard breakdown and it is independent with the current drive capability of current limiting transistors. Soft breakdown results in very small voltage drop across the current limiting device (i.e. between source and drain terminals), which will have negligible impact on the circuit functionality. It suggests circuit functionality will be immune from gate oxide breakdown in normal circuit operating condition, i.e. Vdd of ∼1V, and designers will get extra reliability margin. Our HSPICE simulation results on ring oscillator (RO) also suggest the logic circuit functionality immunity with gate oxide breakdown.

Re-investigation of frequency dependence of PBTI/TDDB and its impact on fast switching logic circuits

In this paper, frequency dependence of the Positive Bias Temperature Instability (PBTI) and the Time Dependent Dielectric Breakdown (TDDB) at relative high frequency range (1KHz ~ 500MHz) in high-k/metal-gate (HK/MG) NMOS are investigated. An explanation of both dependencies of PBTI and TDDB with capture/emission times is proposed. This paper is divided into three parts: 1) AC PBTI and the existence of critical frequencies is discussed, 2) Frequency dependence of TDDB and its implication of the time to form leakage path, and 3) AC BTI/TDDB impacts on logic circuit, which is studied using simulated frequency degradation of ring oscillators (ROs). Based on the negligible frequency degradation of RO with worst Idsat degradations, we conclude that, for circuits operating in a continuous switching mode, BTI/TDDB will not be an unsurpassable reliability issue.

Investigation of multistage linear region drain current degradation and gate-oxide breakdown under hot-carrier stress in BCD HV PMOS

Hot-carrier injection (HCI) at maximum gate current (IG) stress condition for BCD HVPMOS has been studied. It is found that HCI not only causes linear region drain current degradation and minimizes the operation window, but also degrades the gate oxide (GOX) and may result in GOX breakdown. A multistage IDlin degradation behavior has been observed during HCI stress, which is associated with two competing mechanisms, i.e., interface-state (Nit) generation and electron trapping caused by hot electrons originated from impact ionization. HCI leads to the gate oxide breakdown even at very low e-field of ∼1.5MV/cm across the GOX. TCAD simulation results by placing Nit and negative charges at different location of the device also support a multistage IDlin degradation. It is found that both initial IG and bulk current (IB) are well correlated with GOX time-dependent-dielectric-breakdown (TDDB). In addition, better TDDB has been observed at higher temperature compared to lower temperature, which verifies that GOX breakdown is associated with HCI.

Investigation of monotonous increase in saturation-region drain current during hot carrier stress in N-type Lateral Diffused MOSFET with STI

Monotonous increase of saturation drain current Idsat but linear-region drain current Idlin reduction during hot carrier injection (HCI) stress is observed in N-type Lateral Diffused MOSFET. But the phenomenon of Idsat increase is contrary to what we typically observed during HCI stress. The increase of Idsat has been attributed to the increase of saturation substrate current Ibsat after HCI stress. TCAD simulations showed that the lateral electric field increases under the high gate bias when a significant amount of electron trapping occurs along the STI corner in the drift region. The trapped electrons will change the distribution of localized electric potential and will result in the substrate current Ib increase. It is also observed that the 1st Ib peak at lower Vgs degrades, consistent with the reduction of drain and source current, due to HCI induced electron trapping. In another word, the electron trapping has two competing effects - one is with current degradation at lower Vgs and the other is with the electric field enhancement that causes the Idsat to increase at higher Vgs.

Delay effects and frequency dependence of NBTI with sub-microsecond measurements

Negative Bias Temperature Instability (NBTI) has been one of the major challenges during process development of advanced technology. In this paper, NBTI of High-k/metal gate (HK/MG) in 10nm FinFET technology has been evaluated. For the first time, fast measurements within sub-microsecond (15ns ~ 1μs) delay time have been demonstrated. Such short recovery time (delay time due to measurement) is achieved through built-in current comparator and a simple state machine. In this paper, we investigated the frequency dependence (10MHz ~ 1GHz) and the impacts of short delay time on NBTI. A 1024-DUT array with inverter-like AC stress [1] was constructed to compare the recovery effects between very short (<;<; 1μs) and long (10s) measurement time. Degradation slopes (time exponents) with different measurement delay time exhibit distinct values while similar frequency dependence of NBTI [2] exists in both short and long delay time domains. The key NBTI indices such as voltage acceleration factor (VAF) and activation energy (Ea) were also extracted and compared between test structures.

The impact and implication of BTI/HCI decoupling on ring oscillator

In this study, a novel RO test structure is proposed and demonstrated to decouple the impact of BTI and HCI effect in RO degradation. The frequency dependence of RO degradation is also investigated with wide frequency range (5.5MHz to 700MHz). Detail characterizations of RO degradation revealed that the impact of NBTI on RO degradation is frequency independent. It is found that NBTI lifetime difference is prominent under different stress frequencies on discrete device. However, NBTI induced ID degradation (ΔID) between sub-GHz range is not significant to show a notable frequency dependency feature. On the other hand, nHCI induced RO degradation increases monotonically as frequency goes higher. The more HCI degradation is in RO, the more notable frequency dependence of RO. Even though nHCI becomes severe under high bias, NBTI is still the dominant degradation mechanism of RO. Due to the huge recovery of NBTI, the frequency shift of RO is not as severe as we expected. It further implies time exponent failed to reflect the dominant degradation mechanism of RO.

The impacts of inverter-like transitions on AC TDDB in a fast switching logic circuit

TDDB of High-k/metal gate (HK/MG) based NMOS in 16nm FinFET technology has been evaluated. In this paper, we investigated the impacts of channel current during transient and Vgd assisted recovery during off-state half cycle on TDDB lifetime and voltage acceleration factor (VAF). A 64-DUT array with AC signals on both gate and drain was constructed to make each DUT have inverter-like transitions. Data was also compared between device array and ring oscillators (RO) to inspect the integral influence of oxide breakdown on logic circuit. Results show a) frequency dependence exists regardless DC [1-2] or AC signal applied to drain, b) with the presence of HCI, inverter-like stress still lengthen TDDB lifetime, and c) V, shift due to AC BTI effects should be considered together with AC TDDB in a fast switching logic circuit.

A novel on-die GHz AC stress test methodology for high speed IO application

A new methodology and test circuit for evaluation of device reliability are presented. The stress conditions must emulate the real circuit operation, or similar to product-like environment. Existing methodology might not archive this purpose. In this paper, an on-die wave front generator was established in circuit level. Experiments in this study cover from mechanisms of off state, Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI). Based on the extensive results, strong dependence of reliability to layout effect can be concluded. And the reliability guidelines and recommendations for high speed IO circuit design can be made.

The impact of inverter-like transitions on device TDDB and ring oscillators

Conventional time dependent dielectric breakdown (TDDB) test for discrete device usually ties source and drain together, i.e. Vds = 0V. However, this condition is seldom seen in a switching logic circuit. To mimic the true behavior of a switching device in a circuit, an inverter-like AC TDDB 64-bit test array is constructed. Although this result in not only TDDB and BTI but also the combined effect of HCI, it is more realistic as well. In this paper, we investigated the impacts of HCI during transient and Vgd assisted recovery during off-state half cycle on TDDB and voltage acceleration factor (VAF). Another simple array to catch the collective behavior of a group of devices is ring oscillator (RO). RO itself is easy to be implemented and characterized for high frequency stress. TDDB data sets from discrete device array and ROs are compared to validate each other. Experiment results show a) frequency dependence exists regardless DC [1-2] or AC signal applied to drain, b) with the presence of HCI up to few hundred MHz, drain side de-trapping still lengthen TDDB lifetime. HCI domination might only occur at even higher frequency in GHz realm.

Wafer level test arrays with simple BIST to expedite process development for circuit reliability

Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.