J.R. Shih

Self-heating effect in FinFETs and its impact on devices reliability characterization

The impact of self-heating effect (SHE) on device reliability characterization, such as BTI, HCI, and TDDB, is extensively examined in this work. Self-heating effect and its impact on device level reliability mechanisms is carefully studied, and an empirical model for layout dependent SHE is established. Since the recovery effect during NBTI characterization is found sensitive to self-heating, either changing VT shift as index or adopting μs-delay measurement system is proposed to get rid of SHE influence. In common HCI stress condition, the high drain stress bias usually leads to high power or self-heating, which may dramatically under-estimate the lifetime extracted. The stress condition Vg = 0.6~0.8Vd is suggested to meet the reasonable operation power and self-heating induced temperature rising. Similarly, drain-bias dependent TDDB characteristics are also under-estimated due to the existence of SHE and need careful calibration to project the lifetime at common usage bias.

Re-investigation of gate oxide breakdown on logic circuit reliability

Gate oxide breakdown has been studied in the circuit-like patterns, i.e. e-Fuse arrays and two-stage inverter circuit. It is observed that time-dependent dielectric breakdown (TDDB) lifetime of eFuse chip is larger compared to discrete devices. Gate oxide breakdown study using two-stage inverter circuit (1st-stage I/O N/PMOS worked as current limiting transistors and 2nd-stage core N/PMOS is stressed transistors) reveals that, even by applying a significant high voltage stress (≤ 3×Vdd) on stressed device, the stress device will suffer only soft breakdown not a hard breakdown and it is independent with the current drive capability of current limiting transistors. Soft breakdown results in very small voltage drop across the current limiting device (i.e. between source and drain terminals), which will have negligible impact on the circuit functionality. It suggests circuit functionality will be immune from gate oxide breakdown in normal circuit operating condition, i.e. Vdd of ∼1V, and designers will get extra reliability margin. Our HSPICE simulation results on ring oscillator (RO) also suggest the logic circuit functionality immunity with gate oxide breakdown.

Prediction of NBTI degradation for circuit under AC operation

A model predicting the negative bias temperature instability (NBTI) reliability of high performance nitrided oxides is developed from discrete p-type metal-oxide-semiconductor field effect transistor (PMOSFET) data and verified with ring oscillator degradation in various frequencies for up to 1GHz. Based on the experimental data and the simulation results, hole traps generation is considered to be major factor for AC NBTI degradation. An AC/DC NBTI improvement factor of around 10 has been observed at low frequency of 0.01Hz while it is significantly larger (∼10000) at 1GHz frequency range. It is established that the measurement techniques are very crucial for accurate NBTI reliability estimation.

The study of sensitive circuit and layout for CDM improvement

The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.

Re-investigation of frequency dependence of PBTI/TDDB and its impact on fast switching logic circuits

In this paper, frequency dependence of the Positive Bias Temperature Instability (PBTI) and the Time Dependent Dielectric Breakdown (TDDB) at relative high frequency range (1KHz ~ 500MHz) in high-k/metal-gate (HK/MG) NMOS are investigated. An explanation of both dependencies of PBTI and TDDB with capture/emission times is proposed. This paper is divided into three parts: 1) AC PBTI and the existence of critical frequencies is discussed, 2) Frequency dependence of TDDB and its implication of the time to form leakage path, and 3) AC BTI/TDDB impacts on logic circuit, which is studied using simulated frequency degradation of ring oscillators (ROs). Based on the negligible frequency degradation of RO with worst Idsat degradations, we conclude that, for circuits operating in a continuous switching mode, BTI/TDDB will not be an unsurpassable reliability issue.

Physical origins of plasma damage and its process/gate area effects on high-k metal gate technology

In advanced high-k metal gate (HK/MG) technologies, plasma induced damage (PID) during process is unavoidable and has the potential to degrade device performance and gate dielectrics. In most cases, PID can be simply managed by process optimization but the root cause and relevant solutions remain unclear. In this study, (i) the origin of plasma damage on Hafnium-based gate oxide (HfO2) devices is verified as bulk traps, located near the HK/oxide interface with negligible latent damage. To resolve this PID issue, we (ii) justify that it can be significantly diminished by optimized post gate etching plasma and improved gate oxide robustness. Moreover, (iii) a quantitative PID model, for the first time, is successfully demonstrated for the incorporated gate area effect by Ig tail of ~4×105μm2 device area, which reduces admissible antenna area for large gate areas in design rule. Gate area scaling is also validated to be crucial for plasma charging damage.

Investigation of multistage linear region drain current degradation and gate-oxide breakdown under hot-carrier stress in BCD HV PMOS

Hot-carrier injection (HCI) at maximum gate current (IG) stress condition for BCD HVPMOS has been studied. It is found that HCI not only causes linear region drain current degradation and minimizes the operation window, but also degrades the gate oxide (GOX) and may result in GOX breakdown. A multistage IDlin degradation behavior has been observed during HCI stress, which is associated with two competing mechanisms, i.e., interface-state (Nit) generation and electron trapping caused by hot electrons originated from impact ionization. HCI leads to the gate oxide breakdown even at very low e-field of ∼1.5MV/cm across the GOX. TCAD simulation results by placing Nit and negative charges at different location of the device also support a multistage IDlin degradation. It is found that both initial IG and bulk current (IB) are well correlated with GOX time-dependent-dielectric-breakdown (TDDB). In addition, better TDDB has been observed at higher temperature compared to lower temperature, which verifies that GOX breakdown is associated with HCI.

The positive trigger voltage lowering effect for latch-up

In this paper, a new latch-up phenomenon, in which the positive trigger voltage V/sub trg+/ is smaller than the theoretical value, based on the two-step activation diode model, is found and analyzed by TCAD simulation. Based on the simulation result, an analytical model for the positive trigger point is developed and methodologies for evaluating the positive trigger point, varying with the geometry layout of the latch-up test patterns, are proposed. The calculated positive trigger current and trigger voltage fit the measurement results very well, so that the proposed method is efficient for evaluating the positive triggering point.

Investigation of monotonous increase in saturation-region drain current during hot carrier stress in N-type Lateral Diffused MOSFET with STI

Monotonous increase of saturation drain current Idsat but linear-region drain current Idlin reduction during hot carrier injection (HCI) stress is observed in N-type Lateral Diffused MOSFET. But the phenomenon of Idsat increase is contrary to what we typically observed during HCI stress. The increase of Idsat has been attributed to the increase of saturation substrate current Ibsat after HCI stress. TCAD simulations showed that the lateral electric field increases under the high gate bias when a significant amount of electron trapping occurs along the STI corner in the drift region. The trapped electrons will change the distribution of localized electric potential and will result in the substrate current Ib increase. It is also observed that the 1st Ib peak at lower Vgs degrades, consistent with the reduction of drain and source current, due to HCI induced electron trapping. In another word, the electron trapping has two competing effects - one is with current degradation at lower Vgs and the other is with the electric field enhancement that causes the Idsat to increase at higher Vgs.

High current characteristics of copper interconnect under transmission-line pulse (TLP) stress and ESD zapping

The Cu metal interconnect under TLP stress can not be treated as the constant current stress. The increase in the metal interconnect length at GGNMOS drain can improve devices MM failure threshold but degrade devices HBM failure threshold and IT2.