Y. S. Tsai

Self-heating effect in FinFETs and its impact on devices reliability characterization

The impact of self-heating effect (SHE) on device reliability characterization, such as BTI, HCI, and TDDB, is extensively examined in this work. Self-heating effect and its impact on device level reliability mechanisms is carefully studied, and an empirical model for layout dependent SHE is established. Since the recovery effect during NBTI characterization is found sensitive to self-heating, either changing VT shift as index or adopting μs-delay measurement system is proposed to get rid of SHE influence. In common HCI stress condition, the high drain stress bias usually leads to high power or self-heating, which may dramatically under-estimate the lifetime extracted. The stress condition Vg = 0.6~0.8Vd is suggested to meet the reasonable operation power and self-heating induced temperature rising. Similarly, drain-bias dependent TDDB characteristics are also under-estimated due to the existence of SHE and need careful calibration to project the lifetime at common usage bias.

Prediction of NBTI degradation for circuit under AC operation

A model predicting the negative bias temperature instability (NBTI) reliability of high performance nitrided oxides is developed from discrete p-type metal-oxide-semiconductor field effect transistor (PMOSFET) data and verified with ring oscillator degradation in various frequencies for up to 1GHz. Based on the experimental data and the simulation results, hole traps generation is considered to be major factor for AC NBTI degradation. An AC/DC NBTI improvement factor of around 10 has been observed at low frequency of 0.01Hz while it is significantly larger (∼10000) at 1GHz frequency range. It is established that the measurement techniques are very crucial for accurate NBTI reliability estimation.

A new on-state drain-bias TDDB lifetime model and HCI effect on drain-bias TDDB of ultra thin oxide

For the first time, a new drain-bias TBD lifetime model is proposed to precisely predict at various Vd, Vg and channel length for ultra thin oxide. The TBD lifetime with drain-bias can be decoupled to small voltage drop at drain-side increased TBD lifetime and hot carrier effect (HCI) degraded the TBD lifetime. The mechanism of oxide breakdown with drain-bias is also well understood as oxide traps distributed from the source side to the center of channel induce the oxide breakdown.

Reliability Assessment of the Embedded DRAM Technology with PMOSFET Transfer Transistor and High-K Dielectrics (Ta2O5) MIM Capacitor

In this paper, wafer level and product level reliability characteristics of embedded DRAM technology with high-K dielectric Ta 2O5 MIM capacitors have been analyzed. It is found although hot carrier injection can induce more apparent gate-induced-drain-leakage (GIDL) current than off-state bias temperature (BT) stress docs, BT stress still dominate the failure bit count increase in real circuit operation. In addition, it is also found the competition between gate-induced-drain-leakage (GIDL) current and the MIM dielectric leakage dominate the failure bit count (FBC) evolution behavior after reliability stress. With transistor doping profile optimization, a new phenomenon of FBC reduction with burn-in time can be observed, and it is attributed to the leakage reduction of MIM capacitor with high-K dielectric Ta2O5 after stress

Modeling of BTI-aging V T stability for advanced planar and FinFET SRAM reliability

In this study, the comparison of time-zero Vt and Bias-Temperature Instability (BTI) induced Vt shift on advanced planar (20nm System-on-Chip, 20SoC) and FinFET (16nm FinFET, 16FF) is investigated, which is modeled by Dispersive Skellam (DS) cumulative distribution framework. As a result of the much better time-zero Vt mismatch and less VT shift spread in FinFET devices, the SRAM static noise margin (SNM) shift distribution of 16FF is less than 20SoC planar technology node. We present a universal picture of time-zero Vt and BTI-aging VT shift management to correlate SRAM bit cell SNM shift, which offers a prospected approach for advanced planar and FinFET SRAM reliability optimization.

The physical mechanism investigation between HK/IL gate stack breakdown and time-dependent oxygen vacancy trap generation in FinFET devices

In this paper, the detailed TDDB models of HK/IL gate stack for N/PMOS were established through the analysis of oxide trap generation in FinFET technology. We systematically characterized gate oxide traps of HK and IL layers by AC admittance and SILC spectrum methodologies. We found that the generation of deep traps in HK layer plays the decisive role in NMOS TDDB, while the formation of deep traps in IL and HK layers are critical to PMOS TDDB. In addition, the deep traps in HK/IL gate stack were found to be highly responsible for the permanent damage during stress, such that, the physical mechanisms of HK/IL gate stack breakdown in FinFET devices can be successfully explained through the time-dependent HK and IL trap generations. From this trap studies, we demonstrated that TDDB reliability of FinFET technology can be improved through the reduction of deep traps.

The physical explanation of TDDB power law lifetime model through oxygen vacancy trap investigations in HKMG NMOS FinFET devices

In this paper, the physical explanation of the time dependent dielectric breakdown (TDDB) power law lifetime model is successfully interpreted through the analysis of oxide trap generation in HK/IL gate stack in NMOS-FinFET technology. The experiments are performed using the stress induced leakage current (SILC) spectrum methodology. It is found that the TDDB power law model has a strong correlation to deep trap generation. Shallow traps, on the other hand, play a role in the increase of SILC behavior and also promote further deep trap formation during the gate oxide degradation. In addition, temperature dependent and recovery voltage dependent TTDB studies reveal that, the deep trap generation is responsible for the permanent damage and the formation of percolation path during the gate oxide degradation. Through the oxygen trap study, the physics of TDDB power law lifetime model can be successfully explained.

A CDM-like damage mechanism for multiple power domains fabricated with Deep N-well processes

In this paper, a mechanism of CDM (Charged-Device Model) — like damage is observed across separated power domain interfaces fabricated with DNW (Deep N-well) processes. This mechanism is modeled and validated by test patterns in a 40nm logic process and by SPICE simulation. The damage mechanism is found to be unlike the traditional CDM and can be observed in wafer form, which means that such damage should be generated during the chip fabrication process. Prevention of damage is proposed and verified.

A New Phenomenon of Retention Time Evolution in Embedded DRAM Technology with High-K Dielectrics (Ta2O5) MIM Capacitor After HTOL Test

In this paper, a new phenomenon regarding to failure bit count (FBC) distribution and data retention time of embedded DRAM with high-K dielectric Ta2O5 MIM capacitors has been observed and explored. Different from conventional knowledge with FBC increase or retention time reduction of DRAM after burn-in, it is found FBC decreased and retention time increased in the sub-0.1mum embedded DRAM technology with high-K dielectric Ta2O5 MIM capacitors. Although the band-to-defect tunneling (BDT) induced junction leakage currents of cell transistors under hot carrier injection (HCI) and off-state bias-temperature (BT) stress will be enhanced, which degrade the FBC and retention time performance. However, it was found the leakage current reduction of high-K dielectric Ta2O5 capacitor after burn-in dominates the FBC reduction and retention time increase

Drain biased TDDB lifetime model for ultra thin gate oxide

For drain biased TDDB, hole injection enhanced gate oxide degradation has been discussed and modeled, and the model is in excellent agreement with the experimental data. Although hole injection will degrade gate oxide, lifetime of drain biased TDDB is better than gate bias due to stress area difference and strong area dependence (/spl beta/ is small) for ultra thin gate oxide; however, it may become a concern for thick oxide for drain bias.