Jian-Hsing Lee

Self-heating effect in FinFETs and its impact on devices reliability characterization

The impact of self-heating effect (SHE) on device reliability characterization, such as BTI, HCI, and TDDB, is extensively examined in this work. Self-heating effect and its impact on device level reliability mechanisms is carefully studied, and an empirical model for layout dependent SHE is established. Since the recovery effect during NBTI characterization is found sensitive to self-heating, either changing VT shift as index or adopting μs-delay measurement system is proposed to get rid of SHE influence. In common HCI stress condition, the high drain stress bias usually leads to high power or self-heating, which may dramatically under-estimate the lifetime extracted. The stress condition Vg = 0.6~0.8Vd is suggested to meet the reasonable operation power and self-heating induced temperature rising. Similarly, drain-bias dependent TDDB characteristics are also under-estimated due to the existence of SHE and need careful calibration to project the lifetime at common usage bias.

A Simple and Useful Layout Scheme to Achieve Uniform Current Distribution for Multi-Finger Silicided Grounded-Gate NMOS

The influence of the contact-to-contact space on the ESD performance of multi-finger silicided ground-gate NMOS (GGNMOS) is investigated. We find that the conventional contact layout, which has short contact-to-contact space, induces current localization, and degrade the device ESD performance. Here we discuss how to design a ballast resistor for silicided multi-finger GGNMOS and show that lengthening the contact spacing can significantly improve device ESD performance (It2, HBM and MM). This improvement eliminates the short channel induced degradation of thin oxide device ESD

The failure mechanism of high voltage tolerance IO buffer under ESD

In this paper, real-time I-V measurements and TCAD simulations were used to study why the ESD performance of the HVT I/O circuit is different from that of the ST NMOS device. The real-time I-V measurements show that the top gate induced voltage of the ST NMOS in HVT I/O circuits under an ESD zapping event is much higher than that of the ST NMOS device. The simulations show that high gate voltage will induce current crowding in the channel region, so as to degrade the device ESD performance. This phenomenon is called gate voltage-induced current crowding (GVICC). However, it is also found that the use of non-silicide S/D structures and increasing RPO dimensions at the drain region of the top NMOSFET can effectively reduce the GVICC effect and induce the currents to flow through the bulk parasitic bipolar transistor. As a result, the ESD failure threshold can be much improved.

Prediction of NBTI degradation for circuit under AC operation

A model predicting the negative bias temperature instability (NBTI) reliability of high performance nitrided oxides is developed from discrete p-type metal-oxide-semiconductor field effect transistor (PMOSFET) data and verified with ring oscillator degradation in various frequencies for up to 1GHz. Based on the experimental data and the simulation results, hole traps generation is considered to be major factor for AC NBTI degradation. An AC/DC NBTI improvement factor of around 10 has been observed at low frequency of 0.01Hz while it is significantly larger (∼10000) at 1GHz frequency range. It is established that the measurement techniques are very crucial for accurate NBTI reliability estimation.

Physical origins of plasma damage and its process/gate area effects on high-k metal gate technology

In advanced high-k metal gate (HK/MG) technologies, plasma induced damage (PID) during process is unavoidable and has the potential to degrade device performance and gate dielectrics. In most cases, PID can be simply managed by process optimization but the root cause and relevant solutions remain unclear. In this study, (i) the origin of plasma damage on Hafnium-based gate oxide (HfO2) devices is verified as bulk traps, located near the HK/oxide interface with negligible latent damage. To resolve this PID issue, we (ii) justify that it can be significantly diminished by optimized post gate etching plasma and improved gate oxide robustness. Moreover, (iii) a quantitative PID model, for the first time, is successfully demonstrated for the incorporated gate area effect by Ig tail of ~4×105μm2 device area, which reduces admissible antenna area for large gate areas in design rule. Gate area scaling is also validated to be crucial for plasma charging damage.

The influence of decoupling capacitor on the discharge behavior of fully silcided power-clamped device under HBM ESD event

In this paper, a new electrostatic-charge discharge (ESD) phenomenon is found. It occurs at the power pad during the human-body model (HBM) zapping event. We call this new ESD phenomenon as the charged capacitor model (CCM). Unlike the IO pad under the HBM event, the power pad under the HBM zapping event doesnt behave the same with IO pad if it is in parallel with a large decoupling capacitor. Before the power-clamped device (Pdev) turns on, the charges will flow from the HBM discharge head to the decoupling capacitor below the power line. After the Pdev turns on, the decoupling capacitor will discharge its stored charges to give the additional stress current to the Pdev. Compared to the HBM event, the rising time of the CCM is much shorter since the decoupling capacitor is connected to the Pdev by a metal bus line. Under such short rising time pulse, only few regions of the device can be turned on to discharge the charges, resulting in the HBM failure threshold voltage of the power pad much smaller than the desired voltage level.

High current characteristics of copper interconnect under transmission-line pulse (TLP) stress and ESD zapping

The Cu metal interconnect under TLP stress can not be treated as the constant current stress. The increase in the metal interconnect length at GGNMOS drain can improve devices MM failure threshold but degrade devices HBM failure threshold and IT2.

Consideration of BTI variability and product level reliability to expedite advanced FinFET process development

In this study, the variability of conventional planar (20nm System-on Chip, 20SoC) and FinFET (16nm FinFET, 16FF) time-zero Vt and Bias-Temperature Instability (BTI) induced aging is investigated, as well as its impact on SRAM and Logic product reliability. For 16FF, the Vt after aging is dominated by initial Vt distribution rather than BTI induced Vt shift, and their Vt sigmas are also superior to planar 20SoC. NBTI (Negative Bias Temperature Instability) relaxation between 20SoC and 16FF are comparable, while 16FF shows less PBTI (Positive Bias Temperature Instability) recovery due to the local high field on fin top. Correlation between SRAM static noise margin (SNM) and NBTI induced Vt shift concurs with the domination of initial Vt sigma for SNM drift. Chip and bit level High-Temperature Operating Life (HTOL) burn-in test with recovery phases demonstrates all the recovery occurs right after stress, so there is no Vt mismatch to make more Vmin tailing. Bit level AC and DC HTOL Vmin sigma concurs with the additional Vt mismatch by DC stress. Logic Vmin recovery at higher temperature demonstrates the signature of BTI contribution in Vmin. These results indicate that even some of the BTI features of 16FF are different from 20SoC, the adequate process optimization for initial Vt sigma tightening still dominates SRAM/Logic HTOL Vmin shift rather than BTI aging.

Low-side driver's failure mechanism in a class-D amplifier under short circuit test and a robust driver device

The failure mechanism in a class-D audio amplifier under short-circuit test is analyzed. The damage, always in the low-side driver, is due to high current induced thermal run-away, which occurs during the shutdown after the over-current is detected. However, this high current doesnt come from the over-current itself since the current is limited to below that the transistor in the class-D amplifier can sustain. Instead, the damage is caused by the displacement current when there is a large voltage change at the output of the class-D amplifier. Although the shutdown circuit is designed to prevent the high current flowing through the transistors of the class-D amplifier, it cannot prevent the current coming from the class-D amplifier itself. To eliminate the damage, the output transistors should be designed robust enough to against the low-pass filter induced large voltage swing.

The dynamic thermal behavior of silicided polysilicon under hight current stress event

A simple dynamic thermal model considering Joule-heating, heatconduction and energy conservation has been developed. It fits the dynamic thermal behavior of the silicided polysilicon under the high current stress event very well. The criterion to induce the DC resistance change of a silicided polysilicon resistor is determined by the phase transform temperature (PTT) of the silicide polysilicon.