Yan Lin Aung

Compiler-assisted technique for rapid performance estimation of FPGA-based processors

This paper proposes a compiler-assisted technique to rapidly estimate performance of a wide range of FPGA processors without requiring actual execution on target processor or ISS. Experimental results show that this technique estimates performance of a widely-used FPGA processor with an average error of 2% in the order of seconds.

Real-Time Image Resizing Hardware Accelerator for Object Detection Algorithms

This paper describes motivation and hardware architecture for resizing input image frames from the camera in order to support real-time scale-invariant object recognition. Conventional implementation of object detection algorithms such as histogram of oriented gradients (HOG) based feature extraction, face detection using Haar classifiers often perform image resizing during the object recognition process. Our investigation reveals that this incurs significant performance overhead due to frequent memory accesses that are required for image resizing. This has motivated our approach to perform online resizing - simultaneously resizing of the input image when it is loaded into frame buffer memory - prior to the object recognition process. We propose a hardware architecture to accelerate image resizing and describe a hybrid processor-accelerator platform to generate different sizes of an image in real-time for object recognition.

Performance estimation framework for FPGA-based processors

Modern FPGA devices can implement a variety of processors with numerous configurable options. Rapid performance estimation of FPGA processors plays a vital role in embedded systems design to select a processor that best fits the application requirements. Traditional performance evaluation techniques such as running the software application on the target processor or using cycle accurate instruction set simulator are time-consuming and poses a threat in meeting the stringent time-to-market pressure. In this paper, we propose a framework to rapidly estimate the performance of a wide range of FPGA processors. The proposed method relies on the LLVM compiler infrastructure and its backend code generator to accurately estimate the software performance within seconds. Experimental results show that the proposed framework can reliably estimate the performance of a widely used FPGA processor with an average accuracy of over 90% for a number of benchmark applications.

C-based design methodology for FPGA implementation of clustalW MSA

Systolisation of the pairwise distance computation algorithm and mapping into field programmable gate arrays (FPGA) have proven to give superior performance at a lower cost, compared to the same algorithm running on a cluster of workstations. The primary design methodology for this approach is based on the hardware description languages such as VHDL and Verilog HDL. An alternative design methodology, however, is the use of a high level language such as C to describe the algorithms and generate equivalent hardware descriptions for implementation in FPGA so as to reduce time to market. This paper describes the design and implementation of the ClustalW first stage multiple sequence alignment based on the Smith-Waterman algorithm on a low cost FPGA development platform using a C language development tool suite. Performance evaluation results show that comparable performance could be achieved to that of Pentium 4 systems and other HDL-based solutions using even the smallest commercially available FPGA device with this design methodology.

Hardware-Software Codesign of EKF-Based Motor Control for Domain-Specific Reconfigurable Platform

This paper presents hardware-software code sign of Extended Kalman Filter (EKF) based motor control for a domain specific reconfigurable platform, which consists of a processor for automotive applications and an FPGA for application specific customization. Considering the existing MISRA C compliant software harnessing dedicated on chip peripherals, we employ a code sign methodology aiming to enable product differentiation through modest hardware accelerator implementation in the reconfigurable logic thus meeting the application constraints under tight time to market pressure. A key step in the design methodology for reducing the effort of hardware customization lies in platform-aware hardware-software partitioning, which takes into accounts communication overhead between the various computing elements. We show that our approach can effectively identify a suitable candidate for hardware acceleration embracing domain specific characteristics and existing standard compliant software.

Microprocessor-based systems design teaching platform for undergraduate students in computer engineering

This paper describes a teaching platform that comprises a commercial FPGA-based board called the DE0 and a custom complementary circuit board of our design called Teaching Auxiliary Board (TAB). The combination contains an ARM Cortex-M1 soft-core processor, numerous analogue and digital peripherals, different types of memory and a Cortex-M3 highly-integrated microcontroller. The deliberate intention was to support laboratory experiments related to embedded systems design in a manner that was of greater educational benefit than using commercial products alone. The content of three core courses in the BEng degree programme for Computer Engineering is outlined to show the context in which the DE0/TAB platform is used. Thereafter, the purpose and expectations of five 2-hour laboratory sessions are presented in detail to illustrate the range of topics to which the platform can be applied.

Area-time estimation of C-based functions for design space exploration

Rapid evaluation of design metrics is essential for hardware-software co-design of hybrid systems on FPGAs. However, acquisition of design metrics from high-level programs is costly and/or time-consuming, and this prohibits rapid design space exploration. We will present a rapid area-time estimation technique that is capable of obtaining hardware design metrics of all the functions of the given C-based application in a fraction of the time required by FPGA implementation. We will demonstrate the proposed area-time estimation technique as part of an open source high-level synthesis tool. For the application considered, we show that the proposed method, which takes into account the effects of hardware binding during estimation, leads to a reduction in estimation error of more than 35 and 8 times for Altera Cyclone II and Stratix IV FPGA respectively.

Reconfigurable smart water quality monitoring system in IoT environment

Since the effective and efficient system of water quality monitoring (WQM) are critical implementation for the issue of polluted water globally, with increasing in the development of Wireless Sensor Network (WSN) technology in the Internet of Things (IoT) environment, real time water quality monitoring is remotely monitored by means of real-time data acquisition, transmission and processing. This paper presents a reconfigurable smart sensor interface device for water quality monitoring system in an IoT environment. The smart WQM system consists of Field Programmable Gate Array (FPGA) design board, sensors, Zigbee based wireless communication module and personal computer (PC). The FPGA board is the core component of the proposed system and it is programmed in very high speed integrated circuit hardware description language (VHDL) and C programming language using Quartus II software and Qsys tool. The proposed WQM system collects the five parameters of water data such as water pH, water level, turbidity, carbon dioxide (CO2) on the surface of water and water temperature in parallel and in real time basis with high speed from multiple different sensor nodes.

Rapid estimation of DSPs utilization for efficient high-level synthesis

High-level synthesis tools are increasingly adopted for designing complex applications on FPGAs. These tools necessitate fast and accurate estimation of FPGA resources in order to produce good design solutions while minimizing design time. Multiplication operations are very commonly found in signal processing, communication, video and image processing applications. In this paper, we present a rapid technique to estimate DSPs utilization for different types of multiplication operations during high-level synthesis. The proposed technique models the synthesis inferences and optimizations performed by state-of-the-art FPGA design tool in order to reliably estimate the number of DSPs and associated LUTs cost of multiplication operations.

Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration

Advancement in design tools is necessary to bridge the widening productivity gap between hardware design and software development in state-of-the-art Field Programmable Gate Arrays (FPGA). We present a design exploration framework that automatically compiles C applications to realize efficient custom co-processor structures for hardware acceleration on the reconfigurable logic. We show that the proposed design exploration framework can automatically generate Register Transfer Level (RTL) codes from C-functions that outperform the commercial Altera C2H RTL generator by about 40% in terms of average area-time product.