Meiqing Wu

Nonparametric Technique Based High-Speed Road Surface Detection

It has been well recognized that detecting road surface in a realistic environment is a challenging problem that is also computationally intensive. Existing road surface detection methods attempt to fit the road surface into rigid models (e.g., planar, clothoid, or B-Spline), thereby restricting to road surfaces that match specific models. In addition, the curve-fitting strategies employed in such techniques incur high computational complexity, making them unsuitable for in-vehicle deployments. In this paper, we propose an efficient nonparametric road surface detection algorithm that exploits the depth cue. The proposed method relies on four intrinsic road scene attributes observed under stereo geometry and has been shown to reliably detect both planar and nonplanar road surfaces efficiently. Extensive evaluations are performed on three widely used benchmarks (i.e., enpeda, KITTI, and Daimler), encompassing many complex road scenarios. The experimental results show that the proposed algorithm significantly outperforms the well-known techniques both in terms of detection accuracy and runtime performance.

Low-complexity pruning for accelerating corner detection

In this paper, we present a novel and computationally efficient pruning technique to speed up the Shi-Tomasi and Harris corner detectors. The proposed technique quickly prunes non-corners and selects a small corner candidate set by approximating the complex corner measure of Shi-Tomasi and Harris. The actual corner measure is then applied only to the reduced candidate set. Experimental results on the NiOS-II platform show that the proposed technique achieves an average execution time savings of 90% for Shi-Tomasi and 70% for Harris detectors for 500 corners with no loss in accuracy.

Real-Time Image Resizing Hardware Accelerator for Object Detection Algorithms

This paper describes motivation and hardware architecture for resizing input image frames from the camera in order to support real-time scale-invariant object recognition. Conventional implementation of object detection algorithms such as histogram of oriented gradients (HOG) based feature extraction, face detection using Haar classifiers often perform image resizing during the object recognition process. Our investigation reveals that this incurs significant performance overhead due to frequent memory accesses that are required for image resizing. This has motivated our approach to perform online resizing - simultaneously resizing of the input image when it is loaded into frame buffer memory - prior to the object recognition process. We propose a hardware architecture to accelerate image resizing and describe a hybrid processor-accelerator platform to generate different sizes of an image in real-time for object recognition.

Threshold-Guided Design and Optimization for Harris Corner Detector Architecture

High-speed corner detection is an essential step in many real-time computer vision applications, e.g., object recognition, motion analysis, and stereo matching. Hardware implementation of corner detection algorithms, such as the Harris corner detector (HCD) has become a viable solution for meeting real-time requirements of the applications. A major challenge lies in the design of power, energy and area efficient architectures that can be deployed in tightly constrained embedded systems while still meeting real-time requirements. In this paper, we proposed a bit-width optimization strategy for designing hardware-efficient HCD that exploits the thresholding step in the algorithm to determine interest points from the corner responses. The proposed strategy relies on the threshold as a guide to truncate the bit-widths of the operators at various stages of the HCD pipeline with only marginal loss of accuracy. Synthesis results based on 65-nm CMOS technology show that the proposed strategy leads to power-delay reduction of 35.2%, and area reduction of 35.4% over the baseline implementation. In addition, through careful retiming, the proposed implementation achieves over 2.2 times increase in maximum frequency while achieving an area reduction of 35.1% and power-delay reduction of 35.7% over the baseline implementation. Finally, we performed repeatability tests to show that the optimized HCD architecture achieves comparable accuracy with the baseline implementation (average decrease of repeatability is less than 0.6%).

A Framework for Fast and Robust Visual Odometry

Knowledge of the ego-vehicle’s motion state is essential for assessing the collision risk in advanced driver assistance systems or autonomous driving. Vision-based methods for estimating the ego-motion of vehicle, i.e., visual odometry, face a number of challenges in uncontrolled realistic urban environments. Existing solutions fail to achieve a good tradeoff between high accuracy and low computational complexity. In this paper, a framework for ego-motion estimation that integrates runtime-efficient strategies with robust techniques at various core stages in visual odometry is proposed. First, a pruning method is employed to reduce the computational complexity of Kanade–Lucas–Tomasi (KLT) feature detection without compromising on the quality of the features. Next, three strategies, i.e., smooth motion constraint, adaptive integration window technique, and automatic tracking failure detection scheme, are introduced into the conventional KLT tracker to facilitate generation of feature correspondences in a robust and runtime efficient way. Finally, an early termination condition for the random sample consensus (RANSAC) algorithm is integrated with the Gauss–Newton optimization scheme to enable rapid convergence of the motion estimation process while achieving robustness. Experimental results based on the KITTI odometry data set show that the proposed technique outperforms the state-of-the-art visual odometry methods by producing more accurate ego-motion estimation in notably lesser amount of time.

Automated thresholding for low-complexity corner detection

Widely-used corner detectors such as Shi-Tomasi and Harris necessitate the selection of a threshold parameter manually in order to identify good quality corners. The recent attempts based on trial-and-error methods for threshold setting are time-consuming, making them unsuitable for low-cost and embedded video processing applications. In this paper we propose a novel automated thresholding technique for Shi-Tomasi and Harris corner detectors based on an iterative pruning strategy. The proposed pruning strategy involves the rapid extraction of potential corner regions and their evaluation for detecting corners. This pruning strategy is applied iteratively until the required number of corners is identified without necessitating the selection of the threshold parameter. As the complex corner measure computations of the Shi-Tomasi and Harris detectors are only applied to very small regions selected by the proposed pruning method, significant savings in computation is also achieved. In addition, the pruning strategy is computationally simpler, making it suitable for deployment in low cost and embedded applications. Our evaluations on the NiOS-II embedded platform show that the proposed automated thresholding technique is able to achieve an average speedup of 67% in Shi-Tomasi and 51% in Harris, with almost no loss in accuracy. The proposed method to identify corners without the manual selection of a threshold parameter makes it ideal for corner detection on a wide range of imagery where the quantity and quality of corners is not known a priori such as in video processing applications.

Vision-based pedestrian tracking system using color and motion cue

Pedestrian tracking is becoming increasingly important for intelligent vehicles to improve the safety on road. Vision based pedestrian tracking with moving cameras faces notorious challenges. The classical background subtraction technique in surveillance applications is no longer applicable for Advanced Driver Assistance Systems (ADASs). In this paper, we propose a vision based pedestrian tracking algorithm which relies on color and motion information. First, pedestrians are detected using the HOG human detector in each image frame. The detected pedestrians are then associated over video frames based on fusion of color-based similarity and motion-based similarity between two image regions. Our studies reveal that the utilization of histogram in the proposed method contributes to high computational complexity. As such, preliminary results for a hardware-efficient implementation of histogram generation and comparison technique have been presented.

Area-Time Efficient FAST Corner Detector Using Data-Path Transposition

Corner detection plays an essential role in many computer vision applications, e.g., object recognition, motion analysis, and stereo matching. In this brief, we present a novel data-path transposition strategy for the hardware design of the FAST corner detector. The proposed design transposes the data-path of the conventional architecture to enable partial evaluation of multiple corners in a pipelined manner, which reduces the size of the window buffer. Further area savings were achieved by combining the operations for computing the corner scores and determining the member vectors. We show that the proposed design on 180-nm CMOS technology leads to about 22% reduction in the critical path delay and lesser area compared to the previously reported architecture, without a notable difference in energy consumption.

Fast and Accurate Pedestrian Detection using Dual-Stage Group Cost-Sensitive RealBoost with Vector Form Filters

Despite significant research efforts in pedestrian detection over the past decade, there is still a ten-fold performance gap between the state-of-the-art methods and human perception. Deep learning methods can provide good performance but suffers from high computational complexity which prohibits their deployment on affordable systems with limited computational resources. In this paper, we propose a pedestrian detection framework that provides a major fillip to the robustness and run-time efficiency of the recent top performing non-deep learning Filtered Channel Feature (FCF) approach. The proposed framework overcomes the computational bottleneck of existing FCF methods by exploiting vector form filters to efficiently extract more discriminative channel features for pedestrian detection. A novel dual-stage group cost-sensitive RealBoost algorithm is used to explore different costs among different types of misclassification in the boosting process in order to improve detection performance. In addition, we propose two strategies, selective classification and selective scale processing, to further accelerate the detection process at the channel feature level and image pyramid level respectively. Experiments on the Caltech and INRIA datasets show that the proposed method achieves the highest detection performance among all the state-of-the-art non-CNN methods and is about 148X faster than the existing best performing FCF method on the Caltech dataset.

Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector

Corner detection plays an essential role in many computer vision applications, e.g., object recognition, motion analysis and stereo matching. Several hardware implementations of corner detection algorithms have been previously reported to meet the real-time requirements of such applications. However, most of the reported implementations adopt similar computational flow which limit their potential for further area-time optimizations. In this paper, we propose a novel hardware design for the FAST corner detector, which unrolls the data-path to perform partial evaluation of multiple corners in a pipelined manner. We then apply logic folding that maximizes the design regularity of the unrolled data-path for resource sharing of the combinational operations. We show that the proposed design on FPGA leads to 20% reduction in critical path delay and about 39% reduction in area-delay product compared to a previously reported architecture. The real-time capability of the proposed FAST corner detectors is demonstrated on the TERASIC DE2i-150 FPGA development kit.