Yang-Hua Chang

Design of multi-finger HBTs with a thermal–electrical model

Abstract Multi-finger heterojunction bipolar transistors (HBTs) with uniform spacing exhibit a higher temperature at the center of devices. The temperature distribution on the emitter fingers of the HBT is studied with a three-dimensional thermal–electrical model. Using this model, multi-finger HBTs are designed with non-uniform spacing to improve temperature distribution. Depending on the number of emitter fingers, different design approaches are demonstrated. For a six-finger or 12-finger HBT, the design is more straightforward. For a complex structure such as a 26-finger HBT, an efficient design procedure is necessary. In all of these cases, the calculated results show significant temperature reduction on non-uniform spacing devices.

A self-consistent extraction procedure for source/drain resistance in MOSFETs

Abstract A new method to determine source/drain series resistance has been developed for MOSFETs operated in linear region. The source/drain resistance ( R SD ) is gate-bias dependent. Channel length reduction (Δ L ) is extracted at low gate bias and chosen to be constant. All parameters extracted in this method are assumed to be independent of mask channel length for model simplicity. The method has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185xa0μm. The extracted parameters are consistent with the assumptions and have been validated by measured I – V characteristics.

Optimization of high voltage LDMOSFETs with complex multiple-resistivity drift region and field plate

An improved high voltage LDMOSFET with multiple-resistivity drift region is proposed. Using the 2-D process simulator TSUPREM4 and device simulator MEDICI, we design a conventional LDMOSFET optimized for breakdown voltage. Then multiple-resistivity drift region is incorporated, with optimized thickness and doping concentration to reduce specific on-resistance while the breakdown voltage is not degraded. To further improve the device performance, we apply a field plate above the drift region to attract more electrons. Carrier concentration in the channel is increased, so drain current level is improved. The simulation result shows that the optimized complex structure, containing both multiple-resistivity drift region and a field plate, exhibits a 34.2% reduction in specific on-resistance with a mere 2.5% degradation of breakdown voltage compared to the standard LDMOSFET.

Design of multi-finger HBTs with a thermal-electrical model

Temperature distribution on the emitter fingers of heterojunction bipolar transistors (HBTs) is studied with a three-dimensional thermal-electrical model. Using this model, multi-finger HBTs is designed with non-uniform spacing. An efficient design procedure is presented. The calculated results show significant temperature reduction on non-uniform spacing devices.

Design of multi-finger AlGaAs/GaAs HBTs with non-uniform spacing

A non-uniform spacing structure in multi-finger heterojunction bipolar transistors is presented to improve thermal stability. Device peak temperature is lowered, and a higher current handling capability can be realized. The design procedures to optimize the spacing are described.

Extraction of bias-dependent parasitic source/drain resistance in MOSFETs with an advanced mobility model

We present a new method to extract gate-bias-dependent source/drain resistance in MOSFETs. The extraction starts from a simple mobility model, but a more sophisticated mobility model is incorporated afterward. The method provides a convenient way to extract the source/drain resistance as well as parameters in a sophisticated mobility model. The extracted parameters in the mobility model vary with channel length. To satisfy some device modeling work where parameters independent of channel length are desirable, we also develop another technique so that a single set of parameters is obtained and is applicable to all channel lengths. The extraction techniques are useful for submicron MOSFETs without going through complicated procedure.

Simulation of electrical characteristics of InP double-heterojunction bipolar transistors with InGaAsSb base

Abstract We study the effect of antimony (Sb) content in the InGaAsSb base layer of InP double-heterojunction bipolar transistors (DHBTs), under the condition of lattice match, by using a two-dimensional device simulator Medici. Careful calibration of physical parameters is first done to ensure that the simulation result matches data measured from a reference device. When the composition of Sb in the InGaAsSb base region is varied, the conduction band offset (Δ E C ), effective density of states in conduction band and valence band ( N C , N V ), bandgap energy ( E G ), and intrinsic carrier concentration ( n i ) are changed accordingly. These semiconductor material parameters are considered in the simulation to compare the electrical characteristics of the DHBT. In addition to the Sb composition, different materials of In 0.52 Al 0.48 As or InP in the emitter are simulated. The study on Sb content in the base and the heterostructure of E–B junction helps the development and optimization of InGaAsSb DHBTs.

Extraction of VBIC model parameters for InGaAsSb DHBTs

This paper presents the extraction procedure of VBIC model parameters for an InGaAsSb DHBT, including the determination of thermal resistance. Unlike conventional GaAs-based HBTs in which thermal resistance can be measured with negligible avalanche effect, the InGaAsSb DHBT under test has both thermal and avalanche effects in the same low-biasing range. Using regular measurement techniques of thermal resistance induces a great error. We have developed a procedure to overcome the problem. The VBIC model showed excellent agreement with the experimental result.

A drain current model for MOSFET's with pocket implantation

A physics-based drain current model with short-channel effect and reverse short-channel effect in pocket-implanted MOSFETs has been developed. The model is able to predict the effect of the pocket implant on threshold voltage and drain current in linear and saturated regions. The validity of the model has been verified by measurement and simulation. This result is beneficial to optimization of implant dosage during processing.

Hybrid stamping and laser micromachining process for micro-scale hole drilling

ABSTRACT Micro-scale hole drilling on metallic sheets has been employed in a wide range of personal computing devices, such as smart phones and tablet computers. Laser machining, micro-electro-discharge machining, and chemical etching are the methods used for fabricating micro-scale holes. In this paper, we propose a hybrid sequential stamping and laser machining process. The alignment in the hybrid process is critical, and a patented device called the ball-cone-hole magnet was used in the experiments to achieve an alignment error of less than 1u2009µm. The fabrication results obtained by laser-only, stamping-only, and the proposed hybrid process were compared. The diameters of inlets and outlets, as well as the cross-section of holes, were compared herein. The surface roughness of the sidewalls’ inside holes was measured. The proposed hybrid stamping and laser machining process provides an alternative fabrication method for the micro-scale hole drilling process with better hole quality than a laser-only machining process.