Yang Yintang

A novel low-voltage low-power bulk-driven cascade current mirror

A novel low-voltage low-power PMOS cascade current mirror employing the bulk-driven technique is described in this paper. Based on SMIC 0.18µm CMOS process, the characteristics of the low-voltage bulk-driven cascade current mirror are analyzed and validated, including the input/output resistance, the system dc transmission error, the frequency characteristics and noise performance, etc. The simulation results reveal that: this bulk-driven cascade current mirror is able to reduce the input voltage drop to 0.3V, and it has the better current driving ability than the gate-driven cascade current mirror does under the same conditions, along with the same good current following characteristic as the gate-driven cascade current mirror. The bulk-driven cascade current mirror achieves the low-voltage low-power characteristic at the cost of the linearity of output current vs input voltage and frequency bandwidth, as well as noise performance. The presented low-voltage bulk-driven cascade current mirror has a good performance for low-frequency low-voltage applications in the design of CMOS analog integrated circuits.

Microtrenching effect of SiC ICP etching in SF6/O2 plasma

Inductively coupled plasma (ICP) etching of single crystal 6H-silicon carbide (SiC) is investigated using oxygen (O2)-added sulfur hexafluoride (SF6) plasmas. The relations between the microtrenching effect and ICP coil power, the composition of the etch gases and different bias voltages are discussed. Experimental results show that the microtrench is caused by the formation of a SiFxOy layer, which has a greater tendency to charge than SiC, after the addition of O2. The microtrenching effect tends to increase as the ICP coil power and bias voltage increase. In addition, the angular distribution of the incident ions and radicals also affects the shape of the microtrench.

Electronic transport properties of the armchair silicon carbide nanotube

The electronic transport properties of the armchair silicon carbide nanotube (SiCNT) are investigated by using the combined nonequilibrium Greens function method with density functional theory. In the equilibrium transmission spectrum of the nanotube, a transmission valley of about 2.12 eV is discovered around Fermi energy, which means that the nanotube is a wide band gap semiconductor and consistent with results of first principle calculations. More important, negative differential resistance is found in its current voltage characteristic. This phenomenon originates from the variation of density of states caused by applied bias voltage. These investigations are meaningful to modeling and simulation in silicon carbide nanotube electronic devices.

Working mechanism of a SiC nanotube NO2 gas sensor

The working mechanism of sensors plays an important role in their simulation and design, which is the foundation of their applications. A model of a nanotube NO2 gas sensor system is established based on an (8, 0) silicon carbide nanotube (SiCNT) with a NO2 molecule adsorbed. The transport properties of the system are studied with a method combining density functional theory (DFT) with the non-equilibrium Greens function (NEGF). The adsorbed gas molecule plays an important role in the transport properties of the gas sensor, which results in the formation of a transmission peak near the Fermi energy. More importantly, the adsorption leads to different voltage current characteristics of the sensor to that with no adsorption; the difference is large enough to detect the presence of NO2 gas.

A high gain wide dynamic range transimpedance amplifier for optical receivers

As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range (DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the −3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the −3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal- lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin- earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 214 m 2 . The design results of this converter show that it

Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.

Effects of microwave pulse-width damage on a bipolar transistor

This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves (HPMs) through the injection approach. The dependences of the microwave damage power, P, and the absorbed energy, E, required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method. A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out. By means of a two-dimensional simulator, ISE-TCAD, the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively. The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different, while only one hot spot exists under the injection of dc pulses. The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy, respectively. The dc pulse damage data may be useful as a lower bound for microwave pulse damage data.

Design of PLL system based Verilog-AMS behavior models

A top-down design method on analog PLL system based Verilog-AMS HDL behavior models is proposed. A PLL contained a VCO behavior model with center frequency 120 MHz and a two-order passive filter with cut-off frequency 300.0 KHz is implemented. The Verilog-AMS behavior models are verified and used in PLL system simulation by the tools of Cadence spectre.

Circuit modeling and performance analysis of SWCNT bundle 3D interconnects

Metallic carbon nanotubes (CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits (ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube (SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional (3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.