Zhu Zhangming

A novel low-voltage low-power bulk-driven cascade current mirror

A novel low-voltage low-power PMOS cascade current mirror employing the bulk-driven technique is described in this paper. Based on SMIC 0.18µm CMOS process, the characteristics of the low-voltage bulk-driven cascade current mirror are analyzed and validated, including the input/output resistance, the system dc transmission error, the frequency characteristics and noise performance, etc. The simulation results reveal that: this bulk-driven cascade current mirror is able to reduce the input voltage drop to 0.3V, and it has the better current driving ability than the gate-driven cascade current mirror does under the same conditions, along with the same good current following characteristic as the gate-driven cascade current mirror. The bulk-driven cascade current mirror achieves the low-voltage low-power characteristic at the cost of the linearity of output current vs input voltage and frequency bandwidth, as well as noise performance. The presented low-voltage bulk-driven cascade current mirror has a good performance for low-frequency low-voltage applications in the design of CMOS analog integrated circuits.

A high gain wide dynamic range transimpedance amplifier for optical receivers

As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range (DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the −3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the −3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal- lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin- earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 214 m 2 . The design results of this converter show that it

Design of PLL system based Verilog-AMS behavior models

A top-down design method on analog PLL system based Verilog-AMS HDL behavior models is proposed. A PLL contained a VCO behavior model with center frequency 120 MHz and a two-order passive filter with cut-off frequency 300.0 KHz is implemented. The Verilog-AMS behavior models are verified and used in PLL system simulation by the tools of Cadence spectre.

An energy-efficient and highly linear switching capacitor procedure for SAR ADCs*

An energy-efficient and highly linear capacitor switching procedure for successive approximation register (SAR) ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VCM-based switching scheme. Moreover, the proposed method shows better linearity than the VCM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18 μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion-step. The measured peak DNL and INL are 0.52/−0.47 LSB and 0.72/−0.79 LSB, respectively, and the peak INL is observed at and , the same as the static nonlinearity model.

Circuit modeling and performance analysis of SWCNT bundle 3D interconnects

Metallic carbon nanotubes (CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits (ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube (SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional (3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.

An offset cancellation technique in a switched-capacitor comparator for SAR ADCs

An offset cancellation technique for a SAR (successive approximation register) ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18 μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to < 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips

In high speed three-dimensional integrated circuits (3D ICs), through silicon via (TSV) insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.

A 10-bit low power SAR A/D converter based on 90 nm CMOS ∗

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is −75 dB, the power supply voltage range is 2.5–5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.