Yann Thoma

The Perplexus bio-inspired reconfigurable circuit

This paper introduces the ubichip, a custom reconfigurable electronic device capable of implementing bio- inspired circuits featuring growth, learning, and evolution. The ubichip is developed in the framework of Perplexus, a European project that aims to develop a scalable hardware platform made of bio-inspired custom reconfigurable devices for simulating large-scale complex systems. In this paper, we describe the configurability and architectural mechanisms that will allow the implementation of evolv- able and developmental cellular and neural systems in an efficient way. These mechanisms are dynamic routing, self- reconfiguration, and a neural-friendly logic cells architecture.

Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot

A cellular hardware implementation of a spiking neural network with run-time reconfigurable connectivity is presented. It is implemented on a compact custom FPGA board, which provides a powerful reconfigurable hardware platform for hardware and software design. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing the network with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the Khepera robot for a task of obstacle avoidance. Finally, future implementations on new multi-cellular hardware are discussed.

Fault Tolerance Using Dynamic Reconfiguration on the POEtic Tissue

Fault tolerance is a crucial operational aspect of biological systems and the self-repair capabilities of complex organisms far exceeds that of even the most advanced electronic devices. While many of the processes used by nature to achieve fault tolerance cannot easily be applied to silicon-based systems, in this paper we show that mechanisms loosely inspired by the operation of multicellular organisms can be transported to electronic systems to provide self-repair capabilities. Features such as dynamic routing, reconfiguration, and on-chip reprogramming can be invaluable for the realization of adaptive hardware systems and for the design of highly complex systems based on the kind of unreliable components that are likely to be introduced in the not-too-distant future. In this paper, we describe the implementation of fault tolerant features that address error detection and recovery through dynamic routing, reconfiguration, and on-chip reprogramming in a novel application specific integrated circuit. We take inspiration from three biological models: phylogenesis, ontogenesis, and epigenesis (hence the POE in POEtic). As in nature, our approach is based on a set of separate and complementary techniques that exploit the novel mechanisms provided by our device in the particular context of fault tolerance.

PERPLEXUS: Pervasive Computing Framework for Modeling Complex Virtually-Unbounded Systems

This paper introduces Perplexus, a European project that aims to develop a scalable hardware platform made of custom reconfigurable devices endowed with bio-inspired capabilities. This platform will enable the simulation of large-scale complex systems and the study of emergent complex behaviors in a virtually unbounded wireless network of computing modules. The final infrastructure will be used as a simulation tool for three applications: neurobiological modeling, culture dissemination modeling, and cooperative collective robotics. The Perplexus platform will provide a novel modeling framework thanks to the pervasive nature of the hardware platform, its bio-inspired capabilities, its strong interaction with the environment, and its dynamic topology.

A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit

In this paper we present a new dynamic routing algorithm specially implemented for a new electronic tissue called POEtic. This reconfigurable circuit is designed to ease the implementation of bio-inspired systems that bring cellular applications into play. Specifically designed for implementing cellular applications, such as neural networks, this circuit is composed of two main parts: a two-dimensional array of basic elements similar to those found in common commercial FPGAs, and a two-dimensional array of routing units that implement a dynamic routing algorithm which allows the creation of data paths between cells at runtime.

POEtic: a prototyping platform for bio-inspired hardware

This paper will present the final hardware realization of a new family of programmable devices that has specifically being conceived in order to address the prototyping of bio-inspired principles. The devices are organized around a custom 32-bit RISC microprocessor and a custom FPGA. The internal architecture devised for the devices is scalable, so that it is possible to construct a physical hardware platform whose size matches the requirements of the application to be handled. To facilitate the development of applications for this hardware platform a complete set of design tools has been developed.

Developmental processes in silicon: an engineering perspective

In this article, we analyze the requirements of developmental processes from the perspective of their implementation in digital hardware. After recalling the motivations for such an implementation, we concentrate separately on the two mechanisms (cellular division and cellular differentiation) that are exploited by biological systems to realize development. We then describe some of the current and projected solutions to implement such mechanisms in hardware, and conclude by analyzing the most interesting features of developmental approaches.

Hardware realization of a bio-inspired POEtic tissue

This paper presents the physical hardware realization of a novel bio-inspired architecture, called POEtic tissue. This electronic tissue provides a platform for the efficient implementation in actual hardware of evolutionary, epigenetic (learning) and ontogenetic (growth, self-repair, self-replication) mechanisms. After a brief introduction the overall organization of the tissue is presented. Then its main building blocks is reviewed. Finally, the implementation details of the first hardware prototype of the tissue, constructed in the form of an ASIC, is outlined. The implementation results demonstrate that the proposed architecture constitutes a good candidate when considering the electronic realization of bio-inspired principles.

A Reconfigurable Chip for Evolvable Hardware

In the recent years, Xilinx devices, like the XC6200, were the preferred solutions for evolving digital systems. In this paper, we present a new System-On-Chip, the POEtic chip, an alternative for evolvable hardware. This chip has been specifically designed to ease the imple- mentation of bio-inspired systems. It is composed of a microprocessor, and a programmable part, containing basic elements, like every standard Field Programmable Gate Array, on top of which sits a special layer im- plementing a dynamic routing algorithm. Online on-chip evolution can then be processed, as every configuration bit of the programmable array can be accessed by the microprocessor. This new platform can therefore replace the Xilinx XC6200, with the advantage of having a processor inside.

MOVE processors that self-replicate and differentiate

This article describes an implementation of a basic multi-processor system that exhibits replication and differentiation abilities on the POEtic tissue, a programmable hardware designed for bio-inspired applications [1,2]. As for a living organism, whose existence starts with only one cell that first divides, our system begins with only one totipotent processor, able to implement any of the cells required by the final organism, which can also fully replicate itself, using the functionalities of the POEtic substrate. Then, analogously to the cells in a developing organism, our just replicated totipotent processors differentiate in order to execute their specific part of the complete organism functionality. In particular, we will present a working realization using MOVE processors whose instructions define the flow of data rather than the operations to be executed [3]. It starts with one basic MOVE processor that first replicates itself three times; the four resulting processors then differentiate and connect together to implement a multi-processor modulus-60 counter.