Yanqing Zhang

A Batteryless 19

This paper presents an ultra-low power batteryless energy harvesting body sensor node (BSN) SoC fabricated in a commercial 130 nm CMOS technology capable of acquiring, processing, and transmitting electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG) data. This SoC utilizes recent advances in energy harvesting, dynamic power management, low voltage boost circuits, bio-signal front-ends, subthreshold processing, and RF transmitter circuit topologies. The SoC is designed so the integration and interaction of circuit blocks accomplish an integrated, flexible, and reconfigurable wireless BSN SoC capable of autonomous power management and operation from harvested power, thus prolonging the node lifetime indefinitely. The chip performs ECG heart rate extraction and atrial fibrillation detection while only consuming 19 μW, running solely on harvested energy. This chip is the first wireless BSN powered solely from a thermoelectric harvester and/or RF power and has lower power, lower minimum supply voltage (30 mV), and more complete system integration than previously reported wireless BSN SoCs.

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Recent advances in ultra-low power chip design techniques, many originally targeting wireless sensor networks, will enable a new generation of body-worn devices for health monitoring. We utilize the state-of-the-art in low power RF transmitters, low voltage boost circuits, subthreshold processing, biosignal front-ends, dynamic power management, and energy harvesting to realize an integrated reconfigurable wireless body-area-sensor node (BASN) SoC capable of autonomous power management for battery-free operation.

W MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications

Body sensor networks (BSNs) are emerging cyber-physical systems that promise to improve quality of life through improved healthcare, augmented sensing and actuation for the disabled, independent living for the elderly, and reduced healthcare costs. However, the physical nature of BSNs introduces new challenges. The human body is a highly dynamic physical environment that creates constantly changing demands on sensing, actuation, and quality of service (QoS). Movement between indoor and outdoor environments and physical movements constantly change the wireless channel characteristics. These dynamic application contexts can also have a dramatic impact on data and resource prioritization. Thus, BSNs must simultaneously deal with rapid changes to both top-down application requirements and bottom-up resource availability. This is made all the more challenging by the wearable nature of BSN devices, which necessitates a vanishingly small size and, therefore, extremely limited hardware resources and power budget. Current research is being performed to develop new principles and techniques for adaptive operation in highly dynamic physical environments, using miniaturized, energy-constrained devices. This paper describes a holistic cross-layer approach that addresses all aspects of the system, from low-level hardware design to higher level communication and data fusion algorithms, to top-level applications.

A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC

A 1 trillion node internet of things (IoT) will require sensing platforms that support numerous applications using power harvesting to avoid the cost and scalability challenge of battery replacement in such large numbers. Previous SoCs achieve good integration and even energy harvesting [1][2][3], but they limit supported applications, need higher end-to-end harvesting efficiency, and require duty-cycling for RF communication. This paper demonstrates a highly integrated, flexible SoC platform that supports multiple sensing modalities, extracts information from data flexibly across applications, harvests and delivers power efficiently, and communicates wirelessly.

Body Sensor Networks: A Holistic Approach From Silicon to Users

Ultra low power (ULP) circuits and energy scavenging mechanisms, though conceptually appealing, have been mainly studied in isolation to date. In this paper, we observe energy harvesting prototypes to derive system-level models and to reveal practical issues specific to various types of energy harvesting systems. Our models predict how design decisions affect overall lifetime. We use our model to derive system driven principles for optimizing architecture, voltage selection, and sub-threshold circuit designs across different types of power harvesting systems.

21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios

We present a synthesizable, sub-threshold, four-channel signal band power extractor for a batteryless body sensor node system on chip (SoC). The power extractor consists of a programmable 30-tap finite impulse response (FIR) filter and signal power circuit (SPC). The filter uses a serial, resource-shared architecture to reduce area, leakage, and power. The FIR supports a programmable number of taps, number of active channels, and coefficient register data. The SPC uses power-of-two arithmetic for reduced complexity, area, and power. The design was synthesized in 130-nm CMOS and consumes 34 nW (32 nW for FIR, 2 nW for SPC) per channel at 350 mV and 29 kHz.

System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms

This paper presents an ultra low power (ULP) solution to hold time closure for subthreshold circuits across PVT variation and mismatch using a two-phase, latch based timing method. We show that compared to conventional hold buffering, our solution saves up to 37% (at 6σ yield) in energy per operation and allows for post tapeout hold time correction. Replacing registers with latches also permits time borrowing, which we show can save up to 47% (6σ yield) when used for setup time closure.

A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC

In this work, we propose a fast tool to compute the variation (σ/μ) of delay for any logic path in a synthesized design for any given process corner. The proposed method does not require deep understanding of device physics, prior knowledge of the design, or extensive Monte Carlo simulation, and it provides good accuracy with less than 11% error. We also demonstrate the importance of using variation estimation methods to identify critical paths in sub-threshold designs, as the logic path with longest nominal delay may not have the greatest stochastic delay (μ+xσ).

Hold time closure for subthreshold circuits using a two-phase, latch based timing method

We present a processor, the Digital Power Manager (DPM), providing power management and node/data/processing flow control for a 130nm battery-less power harvesting body sensor node. The DPM adjusts node power consumption, responding to available energy to support operation exclusively from harvested power. The DPM consumes 2.5pJ/instruction and 0.63pJ/cycle for NOPs.