Yousef Shakhsheer

A Batteryless 19

This paper presents an ultra-low power batteryless energy harvesting body sensor node (BSN) SoC fabricated in a commercial 130 nm CMOS technology capable of acquiring, processing, and transmitting electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG) data. This SoC utilizes recent advances in energy harvesting, dynamic power management, low voltage boost circuits, bio-signal front-ends, subthreshold processing, and RF transmitter circuit topologies. The SoC is designed so the integration and interaction of circuit blocks accomplish an integrated, flexible, and reconfigurable wireless BSN SoC capable of autonomous power management and operation from harvested power, thus prolonging the node lifetime indefinitely. The chip performs ECG heart rate extraction and atrial fibrillation detection while only consuming 19 μW, running solely on harvested energy. This chip is the first wireless BSN powered solely from a thermoelectric harvester and/or RF power and has lower power, lower minimum supply voltage (30 mV), and more complete system integration than previously reported wireless BSN SoCs.

\mu

Recent advances in ultra-low power chip design techniques, many originally targeting wireless sensor networks, will enable a new generation of body-worn devices for health monitoring. We utilize the state-of-the-art in low power RF transmitters, low voltage boost circuits, subthreshold processing, biosignal front-ends, dynamic power management, and energy harvesting to realize an integrated reconfigurable wireless body-area-sensor node (BASN) SoC capable of autonomous power management for battery-free operation.

W MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications

A 1 trillion node internet of things (IoT) will require sensing platforms that support numerous applications using power harvesting to avoid the cost and scalability challenge of battery replacement in such large numbers. Previous SoCs achieve good integration and even energy harvesting [1][2][3], but they limit supported applications, need higher end-to-end harvesting efficiency, and require duty-cycling for RF communication. This paper demonstrates a highly integrated, flexible SoC platform that supports multiple sensing modalities, extracts information from data flexibly across applications, harvests and delivers power efficiently, and communicates wirelessly.

A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC

Batteryless operation and ultra-low-power (ULP) wireless communication will be two key enabling technologies as the IC industry races to keep pace with the IoE projections of 1T-connected sensors by 2025. Bluetooth Low-Energy (BLE) is used in many consumer IoE devices now because it offers the lowest average power for a radio that can communicate directly to a mobile device [1]. The BLE standard requires that the IoE device continuously advertises, which initiates the connection to a mobile device. Sub-1s advertisement intervals are common to minimize latency. However, this continuous advertising results in a typical minimum average power of 10s of μW at low duty-cycles. This leads to the quoted 1-year lifetimes of event-driven IoE devices (e.g. tracking tags, ibeacons) that operate from coin-cell batteries. This minimum power is too high for robust, batteryless operation in a small form-factor.

21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios

This paper presents a batteryless system-on-chip (SoC) that operates off energy harvested from indoor solar cells and/or thermoelectric generators (TEGs) on the body. Fabricated in a commercial 0.13 μW process, this SoC sensing platform consists of an integrated energy harvesting and power management unit (EH-PMU) with maximum power point tracking, multiple sensing modalities, programmable core and a low power microcontroller with several hardware accelerators to enable energy-efficient digital signal processing, ultra-low-power (ULP) asymmetric radios for wireless transmission, and a 100 nW wake-up radio. The EH-PMU achieves a peak end-to-end efficiency of 75% delivering power to a 100 μA load. In an example motion detection application, the SoC reads data from an accelerometer through SPI, processes it, and sends it over the radio. The SPI and digital processing consume only 2.27 μW, while the integrated radio consumes 4.18 μW when transmitting at 187.5 kbps for a total of 6.45 μW.

26.8 A 236nW −56.5dBm-sensitivity bluetooth low-energy wakeup receiver with energy harvesting in 65nm CMOS

This paper presents a 32 b, 90 nm data flow processor capable of executing arbitrary DSP algorithms using fine grained Dynamic Voltage Scaling (DVS) at the component level with rapid V DD switching and V DD dithering for near-ideal quadratic dynamic energy scaling from 0.25 V-1.2 V. This is the first full processor with Panoptic (all-inclusive) DVS, single clock cycle V DD switching, V DD dithering, and the ability to switch between high performance DVS operation and a sub-threshold mode of operation. This paper also explores V DD header switching and voltage selection considerations for additional savings. Measurements show up to 80% and 43% energy savings of using PDVS over single V DD ( SVDD) and multi- V DD ( MVDD), respectively. Additionally, PDVS shows area savings of up to 65% over MVDD given the same energy consumption.

A 6.45

We present a 90nm data flow processor that executes DSP algorithms using fine grained DVS at the component level with rapid V<inf>DD</inf> switching and V<inf>DD</inf> dithering for near-ideal quadratic dynamic energy scaling from 0.25V–1.2V. Measurements show energy savings up to 50% and 46% compared to single-V<inf>DD</inf> and multi-V<inf>DD</inf> alternatives.

\mu{\rm W}

Biological hair fluid motion sensors are found in a variety of animals such as arachnids and marine mammals. These sensors display a wide range of geometrical sizes and dynamic characteristics affecting their sensitivity. We report design revisions to improve sensitivity, wake detection capabilities, and reliability in a biologically inspired fluid motion/wake detection sensor. The design implements a cone-in-cone capacitance based sensing mechanism for monitoring fluid motion fluctuations in the wake of an object in four directions. The improved sensor design shows a gain range (the difference between peak output voltage amplitude divided by the peak input voltage amplitude) of up to 0.27 between whisker compression and deflection, a 300X increase relative to prior art. Improvements to the sensor include adjusting the deflection measurement modality, increasing the inner cone size, using silver epoxy for plating, shielding signal wires, and reducing parasitic capacitance that dampens the output voltage range.

Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems

This work explores optimizing power switch design for Dynamic Voltage Scaling schemes that use headers to connect components to voltage supplies ranging from strong inversion to subthreshold values. We propose using NMOS devices with their gate controlled at the nominal voltage as power switches connected to the subthreshold voltage rail. Measured results show that an NMOS can provide the subthreshold voltage with a power switch size >280X smaller than a PMOS. For architectures targeting operation from subthreshold up to nominal voltage, we show that using an asymmetric transmission gate power switch provides a lower overhead way to enable this flexibility.

A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance

This paper explores the benefits of splitting a monolithic power gate transistor into parallel, independently controlled, variable weighted power gates to provide programmable post-fabrication power grid resistance. This power gate topology creates energy saving opportunities by providing adjustable localized voltages during active modes and reducing leakage current in idle blocks while retaining data. Measurements show over 30% active energy savings per operation and 90% savings in idle current with retention. A modeling flow for a resistive power grid was also developed that demonstrates the effectiveness of this approach in a Bulldozer processor core.