Yao Suying

An Improved Three-Step Search Algorithm with Zero Detection and Vector Filter for Motion Estimation

In this paper, a new fast block matching algorithm is developed for motion estimation. The motion estimation algorithm use improved 3-step block matching (ITSS) algorithm that can produces better quality performance and less computational time compared with three-step search (TSS) algorithm and correct the motion vector by using Zero Detection and vector filter. From the experimental results, the proposed algorithm is superior to TSS in both quality performance and computational complexity.

Noise in a CMOS digital pixel sensor

Based on the study of noise performance in CMOS digital pixel sensor (DPS), a mathematical model of noise is established with the pulse-width-modulation (PWM) principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparators reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS.

Collection efficiency and charge transfer optimization for a 4-T pixel with multi n-type implants

In order to increase collection efficiency and eliminate image lag, multi n-type implants were introduced into the process of a pinned-photodiode. For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed, which expanded the vertical collection region. To reduce the image lag, a horizontal gradient doping concentration eliminating the potential barrier was also formed by multi n-type implants. The simulation result shows that the collection efficiency can be improved by about 10% in the long wavelength range and the density of the residual charge is reduced from 2.59 × 109 to 2.62 × 107cm−3.

Analysis of incomplete charge transfer effects in a CMOS image sensor

A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size. Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction. Further analysis of noise for incomplete charge transfer predicts the noise variation. The test pixels were fabricated in a specialized 0.18 μm CMOS image sensor process and two different processes of buried N layer implantation are compared. The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer. The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.

Development and Implementation of Automatic White Balance Based on Luminance Compensation

Automatic white balance plays a key role in image signal processing circuit of image sensors, and determines image quality to a large extent. An automatic white balance algorithm based on luminance compensation is proposed. The algorithm establish the equations of RGB channels between the captured image and the natural one firstly based on the assumption that the luminance average of the whole image holds the line when the light source has changed. Then, to compensate the loss of luminance that might be made by the primary plus and make the corrected image equal to the natural one, the algorithm further combines the max white method to amend the gains. So the image will be proofread accurately. To evaluate the proposed algorithm, the subjective observation method and the objective comparison method are both used, and the results of the test prove that the corrected results of image emendated by it are excelled to that by some traditional algorithms. Finally, this algorithm is implemented with VLSI design, and the test of integration indicates that the algorithm is easy to be realized in the integrated circuit and can satisfy the requirement of real-time processing.

Simulation and test of a novel SOI high temperature pressure sensor

A novel high temperature pressure sensor is designed by the authors. It is based on a SOI construction, replacing the traditional pn junction insulation with SiO/sub 2/ insulation. The dielectric isolation guarantees low leakage current at high temperature. Thus, the sensors could be used in a high temperature environment. In this paper, a series of SOI high temperature sensors were simulated and analyzed by ANSYS software. The influence of thickness and length-width ratio of the strain diaphragm on the theoretical output was discussed. Accordingly, an optimal design of the strain diaphragm was presented and the location of the piezoresistors was determined. Finally, the sensors were fabricated according to the layout, and then tested. The test results showed that the actual measurement values are consistent with the simulation. The output voltage keeps good linearity with input pressure even at high temperatures. The properties of the product are satisfactory.

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0:12/−0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μW with a 1.8 V supply, and its area is 0.03 × 0.8 mm2.

Lag free transfer transistor in CMOS image sensor pixel with a non-uniform doped gate

A transfer transistor structure achieving complete charge transfer in a CMOS image sensor pixel is proposed to eliminate image lag. This structure adopted double N implants for photodiode to ensure a wide channel of charge transfer, a surface P type preventing from dark current and especially a non-uniform doped poly-silicon gate to adjust the potential profile in channel. The simulation results show that if a light pulse of 10000lux illuminates for one integration cycle, the signal voltage of the following frame drops to 1/50000 of the first one. The electron density in N buried layer after charge transfer is around 108/cm3, far below the intrinsic value.

Pixel Cross-talk Compensation for CMOS Image Sensors

A new algorithm for removing pixel cross-talk effect in CMOS image sensors with Bayer color filter array is proposed. With the assumption that color differences within small neighbors of an image is constant, the algorithm uses the R or B components of raw data to compensate the adjacent G component before color interpolation in order to eliminate the effects that R component interferes with Gr and B component interferes with Gb. The algorithm has low computational complexity. By simulation experimentation on Macbeth color chart and real images, the algorithm is proved to be effective and produces better quality images with conventional color interpolation methods. Finally, the paper design its VLSI frame and validates it with FPGA. The results of test indicate that the algorithm uses fewer hardware resources and can work in real-time completely.

A linear stepping PGA used in CMOS image sensors

A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.