Yaser M. Banadaki

Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology

In this paper, we have investigated the static metrics and switching attributes of graphene nanoribbon field-effect transistors (GNR FETs) for scaling the channel length from 15 nm down to 2.5 nm and GNR width by approaching the ultimate vertical scaling of oxide thickness. We have simulated the double-gate GNR FET by solving a numerical quantum transport model based on selfconsistent solution of the 3D Poisson equation and 1D Schrödinger equation within the non-equilibrium Greens function formulism. The narrow armchair GNR, e.g. (7,0), improved the device robustness to shortchannel effects, leading to better OFF-state performance considering OFF-current, ION/IOFF ratio, subthreshold swing, and drain-induced barrier-lowering. The wider armchair GNRs allow the scaling of channel length and supply voltage, resulting in better ON-state performance, such as the larger intrinsic cut-off frequency for the channel length below 7.5 nm at smaller gate voltage as well as smaller intrinsic gate-delay time with the constant slope for scaling the channel length and supply voltage. The wider armchair GNRs, e.g. (13,0), have smaller power-delay product for scaling the channel length and supply voltage, reaching to ~0.18 (fJ/μm).

A novel graphene nanoribbon field effect transistor for integrated circuit design

In this work, we present a novel structure of Graphene NanoRibbon Field-Effect Transistor (GNR FET) to reduce short channel effects. In this structure, two side metal gates with lower work-function than the main gate are used in a conventional double-gate (DG) GNR FET topology to provide virtual extensions to source/drain regions while these are biased constant, independent of the main gate. The proposed GNR FET structure improves drain-induced barrier lowering (DIBL), which can reduce the short-channel effects (SCE) in device performance such as on/off current ratio, off-state current and subthreshold slope to make it a more suitable configuration than the normal GNR FET for digital integrated circuit design.

Metallic single-walled, carbon nanotube temperature sensor with self heating

A metallic single-walled carbon nanotube (SWCNT) has been proposed as a highly sensitive temperature sensor with consideration of self-heating induced scattering. This sensor can be implemented to sense temperature spanning from 20º C to 400º C with high temperature coefficient of resistivity (TCR) ranging from 0.0035/ºC to 0.009/ ºC. Important aspect of this work is consideration of self-heating in SWCNT which was not considered in earlier carbon nanotube based temperature sensors. We have studied a metallic SWCNT over a silicon dioxide substrate and in between two metal contacts. Bias voltage of 0.1V has been applied in between these two contacts. For resistivity calculation, we have utilized one-dimensional semi-classical transport model assuming SWCNT is perfectly conducting. The heat flow equation has been solved assuming steady state flow of heat. We have also assumed that contact and substrate are in thermal equilibrium with the surroundings. Since self-heating significantly affects electro-thermal transport, incorporation of this phenomenon enables to design and model ambient temperature sensor accurately. We have studied CNT sensor with different lengths and chiralities. The results show that resistances of longest (3μm) and thinnest (9, 0) CNTs increase rapidly with temperature. For a 3μm long metallic SWCNT with chirality index (9, 0), TCR has the maximum value (~0.009/ ºC).

Temperature sensor for monitoring of hot spots in integrated circuits

Aggressive scaling of transistor dimensions and increasing chip complexity have satisfied the demand for increased performance of integrated circuits for many decades. In these ways, the supply voltage and capacitance of the devices can be reduced by scaling down the device dimensions. Small geometry effects, however, play a major role in the degradation of integrated circuit performance levels. These effects cause an increase in the leakage current, and consequently the static power dissipation.1 The power dissipation and corresponding die temperature of integrated circuits have therefore continuously increased. It is known, however, that the scaling limit of silicon (dictated by Moore’s law) will soon be reached.2 As part of an effort to find a suitable substitute for silicon in integrated circuits, a large group of emerging materials is now being extensively studied. Graphene has an atomically thin planar structure, a high carrier concentration, high carrier mobility, and good thermal conductivity.3 These characteristics thus allow for more aggressive supply voltage scaling (along with simultaneously higher drive current) with graphene than with silicon metal-oxide semiconductor (MOS) field-effect transistors (FETs). In addition, a graphene nanoribbon (GNR)—narrow stripes of graphene—is a promising alternative channel material in MOS-type structures. The atomistic calculated thickness of a GNR also provides the maximum possible surface-to-bulk ratio, which enables the design of high-performance temperature sensors.4–7 An all-graphene architecture, in which all the transistors and interconnects can be fabricated from concurrent patterning of a graphene sheet, has recently been proposed.8 Since all the components in this architecture must be made from graphene, we have explored the feasibility of using a thin oxide GNR array as a high-performance temperature sensor for the detection of Figure 1. Schematic diagram of the back-gate multi-channel graphene nanoribbon (GNR) field-effect transistor (FET) temperature sensor device. A vertical cross section of the device is shown in (a) and a 3D view in (b). LG, WG: Graphene length and width, respectively. Wsp: Spacing width. WGNR: GNR width.

Detection of complex molecular samples by low-cost surface enhanced raman spectroscopy (SERS) substrate

Raman scattering is a well-known technique for detecting and identifying complex molecular samples. The weak Raman signals are enormously enhanced in the presence of a nano-patterned metallic surface next to the specimen. This paper reports new techniques to obtain the nanostructures required for Surface Enhanced Raman Scattering (SERS) without costly and sophisticated fabrication steps, which are nanoimprint lithography (NIL), electrochemical deposition, electron beam induced deposition, and focus ion beam (FIB). 20 nm Au thicknesses of sputtered Au were deposited on etched household aluminum foil (base substrate) for vitro application. The Raman signal were caused by the Aluminum pre-etched times. In preliminary results, enhancement factors of 106 times were observed from SERS substrate for in vitro measurements. Moreover, the ability to perform in vivo measurements was demonstrated after removing the base aluminum foil substrate. This application allows Raman signals to be obtained from the surface or interior of opaque specimens. The nano-patterned gold may also be coupled in a probe to a remote spectrometer via an articulated arm. This opens up Raman spectroscopy for use in a clinical environment.

Graphene field effect transistor for generating on-chip thermoelectric power

Graphene is a promising material for thermoelectric application due to its large surface-to-volume ratio, high electrical conductivity, and high mechanical strength. In this paper, the thermoelectric properties of a series of narrow armchair graphene nanoribbons (GNR) in semiconducting family GNR(3p+1,0) are evaluated by using the semi-classical Boltzmann theory. It is found that the narrow GNR(7,0) exhibits small thermal conductivity and large TEP of 1170μV / K at small chemical potential μ = 0.1 eV . However, the small electrical conductivity of narrow GNR(7,0) suppresses the thermoelectric figure-of-merit ZT, such that better thermoelectric performance of ZT > 0.01 is achieved only for large chemical potentials, μ > 0.5eV . Our result shows that tuning the chemical potential with respect to ribbon chirality and orientation can enhance the thermoelectric performance of GNRs, however, further increase in thermoelectric power requires phonon engineering to reduce the thermal conductivity of graphene without significant reduction in its thermoelectric power and electrical conductivity.

Overview of Carbon Nanotube Interconnects

At present, electronic information technology has become an important drive force that promotes social and economic progress. Integrated circuit (IC) as a core and foundation of the electronic information technology has a great influence on the daily life of human being. The semiconductor technology and IC industry have become an important symbol to embody a country’s comprehensive scientific and technological capability. In order to improve circuit’s performance and increase number of transistors on a chip, microelectronic devices have been continuously reduced in dimension according to Moore’s law [1] and scaling rule [2]. According to the 2013 International Technology Roadmap for Semiconductors (ITRS 2013), the feature size of semiconductor devices will reduce to 22 nm in 2016 and 10 nm in 2025 [3] in very large scale integrated (VLSI) circuits. For the first generation interconnect material aluminum (Al) [4], an increase in electric resistance and capacitance due to increasing wire length and decreasing wire interval as dimension scales down had led to large signal delays [5] and poor tolerance to electromigration (EM) [6]. Because of its lower resistivity, higher melting point (1083 °C versus 660 °C of Al), and longer EM lifetime [7], copper (Cu) has replaced Al as an interconnect material in the 180 nm technology node [8] and beyond. But as interconnects scale down to the 45 nm and beyond technology generations, Cu interconnect is also facing similar problems with those of Al interconnects encountered, including increase in resistivity due to size effect [9], increase in power consumption [10], delay [11], and EM distress [12].

Metallic single-walled carbon nanotube for ionized radiation detection

In this paper, we have explored the feasibility of a metallic single-walled carbon nanotube (SWCNT) as a radiation detector. The effect of SWCNTs’ exposure to different ion irradiations is considered with the displacement damage dose (DDD) methodology. The analytical model of the irradiated resistance of metallic SWCNT has been developed and verified by the experimental data for increasing DDD from 1012 MeV/g to 1017 MeV/g. It has been found that the resistance variation of SWCNT by increasing DDD can be significant depending on the length and diameter of SWCNT, such that the DDD as low as 1012 (MeV/g) can be detected using the SWCNT with 1cm length and 5nm diameter. Increasing the length and diameter of SWCNT can result in both the higher radiation sensitivity of resistance and the extension of detection range to lower DDD.

Graphene nanoribbon field effect transistor for nanometer-size on-chip temperature sensor

Graphene has been extensively investigated as a promising material for various types of high performance sensors due to its large surface-to-volume ratio, remarkably high carrier mobility, high carrier density, high thermal conductivity, extremely high mechanical strength and high signal-to-noise ratio. The power density and the corresponding die temperature can be tremendously high in scaled emerging technology designs, urging the on-chip sensing and controlling of the generated heat in nanometer dimensions. In this paper, we have explored the feasibility of a thin oxide graphene nanoribbon (GNR) as nanometer-size temperature sensor for detecting local on-chip temperature at scaled bias voltages of emerging technology. We have introduced an analytical model for GNR FET for 22nm technology node, which incorporates both thermionic emission of high-energy carriers and band-to-band-tunneling (BTBT) of carriers from drain to channel regions together with different scattering mechanisms due to intrinsic acoustic phonons and optical phonons and line-edge roughness in narrow GNRs. The temperature coefficient of resistivity (TCR) of GNR FET-based temperature sensor shows approximately an order of magnitude higher TCR than large-area graphene FET temperature sensor by accurately choosing of GNR width and bias condition for a temperature set point. At gate bias VGS = 0.55 V, TCR maximizes at room temperature to 2.1×10−2 /K, which is also independent of GNR width, allowing the design of width-free GNR FET for room temperature sensing applications.

Carbon Nanotube Ring Oscillator for Detecting Ionized Radiation

In this paper, we have explored the feasibility of a carbon nanotube (CNT) ring oscillator (RO) for detecting ionized radiation. The effect of ion irradiation on the oscillation frequency of CNT-based RO is considered using the displacement damage dose (DDD) methodology. The analytical model of the irradiated resistance of metallic single-walled CNT (SWCNT) has been developed and verified by experimental data for increasing DDD from 10 to 10 MeV/g. We have found that 100 times increase in the DDD from 10 to 10 MeV/g results in nearly 20 times increase in propagation delay of an input signal passing through 500 nm metallic SWCNT, which can be easily read. It is also found that an order of magnitude increase in the length of SWCNT results in approximately an order of magnitude decrease in the minimum range of detectable DDD considering the oscillation frequency of CNT RO as the output of the proposed radiation detector. As carbon nanotube with the record length of 50 cm has been reported, it is very promising for detecting much lower radiation.