Yasin Khatami

Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field Effect Transistors

This work presents a systematic study toward the design and first demonstration of high-performance n-type monolayer tungsten diselenide (WSe2) field effect transistors (FET) by selecting the contact metal based on understanding the physics of contact between metal and monolayer WSe2. Device measurements supported by ab initio density functional theory (DFT) calculations indicate that the d-orbitals of the contact metal play a key role in forming low resistance ohmic contacts with monolayer WSe2. On the basis of this understanding, indium (In) leads to small ohmic contact resistance with WSe2 and consequently, back-gated In-WSe2 FETs attained a record ON-current of 210 μA/μm, which is the highest value achieved in any monolayer transition-metal dichalcogenide- (TMD) based FET to date. An electron mobility of 142 cm(2)/V·s (with an ON/OFF current ratio exceeding 10(6)) is also achieved with In-WSe2 FETs at room temperature. This is the highest electron mobility reported for any back gated monolayer TMD material till date. The performance of n-type monolayer WSe2 FET was further improved by Al2O3 deposition on top of WSe2 to suppress the Coulomb scattering. Under the high-κ dielectric environment, electron mobility of Ag-WSe2 FET reached ~202 cm(2)/V·s with an ON/OFF ratio of over 10(6) and a high ON-current of 205 μA/μm. In tandem with a recent report of p-type monolayer WSe2 FET ( Fang , H . et al. Nano Lett. 2012 , 12 , ( 7 ), 3788 - 3792 ), this demonstration of a high-performance n-type monolayer WSe2 FET corroborates the superb potential of WSe2 for complementary digital logic applications.

Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits

In this paper, novel n- and p-type tunnel field-effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer are proposed, which exhibit very small subthreshold swings, as well as low threshold voltages. The design parameters for improvement of the characteristics of the devices are studied and optimized based on the theoretical principles and simulation results. The proposed devices are designed to have extremely low off currents on the order of 1 fA/mum and engineered to exhibit substantially higher on currents compared with previously reported T-FET devices. Subthreshold swings as low as 15 mV/dec and threshold voltages as low as 0.13 V are achieved in these devices. Moreover, the T-FETs are designed to exhibit input and output characteristics compatible with CMOS-type digital-circuit applications. Using the proposed n- and p-type devices, the implementation of an inverter circuit based on T-FETs is reported. The performance of the T-FET-based inverter is compared with the 65-nm low-power CMOS-based inverter, and a gain of ~104 is achieved in static power consumption for the T-FET-based inverter with smaller gate delay.

Metal-to-Multilayer-Graphene Contact—Part I: Contact Resistance Modeling

Parasitic components are becoming increasingly important with geometric scaling in nanoscale electronic devices and interconnects. The parasitic contact resistance between metal electrodes and multilayer graphene (MLG) is a key factor determining the performance of MLG-based structures in various applications. The available methods for characterizing metal–MLG contact interfaces rely on a model based on the top-contact structure, but it ignores the edge contacts that can greatly reduce the contact resistance. Therefore, in the present work, a rigorous theoretical 1-D model for metal–MLG contact is developed for the first time. The contribution of the major components of resistance—the top and edge contacts (side and end contacts) and the MLG sheet resistivity—to the total resistance of the structure is included in the model. The 1-D model is compared to a 3-D model of the system, and a method for investigation and optimization of the range of validity of the 1-D model is developed. The results of this work provide valuable insight to both the characterization and design of metal–MLG contacts.

Proposal for all-graphene monolithic logic circuits

Since the very inception of integrated circuits, dissimilar materials have been used for fabricating devices and interconnects. Typically, semiconductors are used for devices and metals are used for interconnecting them. This, however, leads to a “contact resistance” between them that degrades device and circuit performance, especially for nanoscale technologies. This letter introduces and explores an “all-graphene” device-interconnect co-design scheme, where a single 2-dimensional sheet of monolayer graphene is proposed to be monolithically patterned to form both active devices (graphene nanoribbon tunnel-field-effect-transistors) as well as interconnects in a seamless manner. Thereby, the use of external contacts is alleviated, resulting in substantial reduction in contact parasitics. Calculations based on tight-binding theory and Non-Equilibrium Greens Function (NEGF) formalism solved self-consistently with the Poissons equation are used to analyze the intricate properties of the proposed structure. ...

High-performance few-layer-MoS 2 field-effect-transistor with record low contact-resistance

Recently, Molybdenum Disulphide (MoS₂) has emerged as a promising candidate for low-power digital applications. Compared to monolayer (1L) MoS₂, few-layer MoS₂ (FL-MoS₂) is attractive due to its higher density of states (DOS). However, a comprehensive study of FL-MoS₂ field-effect-transistor (FET) is lacking. In this paper, we report a high-performance FL-MoS₂ FET with record low contact resistance (~0.8 KΩ.μm) that is close to the value for metal-silicon contacts in CMOS technology. A correlation of device performance and the number of MoS₂ layers is established to guide the design of high-performance FL-MoS₂ FET. Moreover, it is found that edge contacts (metal contact to each edge of MoS₂ layers) play a key role in the efficient injection of electrons from metal to MoS₂. This is confirmed by experiments as well as density functional theory (DFT) calculations. Moreover, a top gated FL-MoS₂ (5 nm) FET is also demonstrated with a robust current saturation and high drive current (24 μA/μm) even without source/drain doping.

Metal-to-Multilayer-Graphene Contact—Part II: Analysis of Contact Resistance

The parasitic contact resistance between metal electrodes and multilayer graphene (MLG) is studied, and the different parameters influencing the contact resistance are investigated. A theoretical model that was developed in the companion paper is applied to typical metal–MLG structures to study the characteristics of the contact. The contributions of all of the three major components of resistance—the top and edge contacts (side and end contacts), the MLG sheet resistivity, and the metal sheet resistivity—to the total resistance are studied. The results show that the total resistance of the metal–MLG contact reduces substantially with the incorporation of edge contacts as the number of graphene layers increases. The current crowding effects are studied with and without consideration of the metal resistivity. Furthermore, the conditions where each of the three major resistance components becomes important are investigated. It is shown that the metal resistance can play an important role in determining the total resistance and current distribution in the contact. The developed model can be used in the characterization and in the design of efficient metal–MLG contact structures. It is shown that, due to the presence of edge contacts, the conventional methods of contact characterization cannot model the metal–MLG structure accurately.

Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications

Negative resistance devices offer opportunities in design of compact and fast analog and digital circuits. However, their implementation in logic applications has been limited due to their small ON current to OFF current ratios (peak to valley ratio). In this paper, a design for a 2-port negative resistance device based on arm-chair graphene nanoribbon is presented. The proposed structure takes advantage of electrostatic doping, and offers high ON current (∼700 μA/μm) as well as ON current to OFF current ratio of more than 105. The effects of several design parameters such as doping profile, gate workfunction, bandgap, and hetero-interface characteristics are investigated to improve the performance of the proposed devices. The proposed device offers high flexibility in terms of the design and optimization, and is suitable for digital logic applications. A complementary logic is developed based on the proposed device, which can be operated down to 200 mV of supply voltage. The complementary logic is used i...

Subthreshold-swing physics of tunnel field-effect transistors

Band-to-band tunnel field-effect-transistors (TFETs) are considered a possible replacement for the conventional metal-oxide-semiconductor field-effect transistors due to their ability to achieve subthreshold swing (SS) below 60 mV/decade. This letter reports a comprehensive study of the SS of TFETs by examining the effects of electrostatics and material parameters of TFETs on their SS through a physics based analytical model. Based on the analysis, an intrinsic SS degradation effect in TFETs is uncovered. Meanwhile, it is also shown that designing a strong onset condition, quantified by an introduced concept - “onset strength”, for TFETs can effectively overcome this degradation at the onset stage, and thereby achieve ultra-sharp switching characteristics. The uncovered physics provides theoretical support to recent experimental results, and forward looking insight into more advanced TFET design.

2D electronics: Graphene and beyond

In this paper, we review the essential physics that lead to the most impressive properties of two-dimensional (2D) nanocrystals, primarily graphene and transition-metal dichalcogenides (TMD). We also highlight some applications uniquely enabled by these 2D materials in the nanoelectronics domain and discuss the related challenges and opportunities.

Graphene based heterostructure tunnel-FETs for low-voltage/high-performance ICs

The characteristics of the wide-narrow GNR T-FET were studied. The proposed device utilizes the small bandgap of wide-GNR to achieve high I<inf>ON</inf> and the high bandgap of narrow-GNR to attain low I<inf>OFF</inf>. The design space for the bandgap/width of the two regions was studied. The design parameters can be optimized to achieve I<inf>ON</inf> as high as 1.3 mA/µm, I<inf>ON</inf>/I<inf>OFF</inf> ratio as high as 10⁹, and S as small as 10 mV/dec at V<inf>DD</inf>=0.5 V. Compared to the HP MOSFET with L<inf>g</inf>=25 nm [6], the wide-narrow GNR T-FET exhibits 2X and 10⁴X improvement in I<inf>ON</inf> and I<inf>ON</inf>/I<inf>OFF</inf> ratio at V<inf>DD</inf>=0.5 V, which makes it suitable for HP/LP applications.