Yassine Aoudni

FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study

With the rapid evolution of technology, the latest FPGA architectures such as Virtex series of Xilinx introduced a new feature called Dynamic Partial Reconfiguration (DPR). This technique allows designer to configure a portion of the FPGA while other parts continue to run on the same FPGA. The design of an embedded system based on the DPR functionality is still complex and tedious. The MPEG consortium proposes the Reconfigurable Video Coding (RVC) technology. RVC provides a high level description of video decoders described as a set of interconnected Functional Units. This paper studies the use of the RVC technology for the specification of an application and the design of a system based on the DPR functionality. In this paper, we study the Inverse Quantization (IQ) algorithm of an MPEG-4 decoder and how to switch between the MPEG-2 and the H263 IQ algorithms using RVC and DPR. This simple and concrete case study highlights the DPR restrictions to take into account in MPEG RVC description in order to use the DPR.

Custom Instruction Integration Method within Reconfigurable SoC and FPGA Devices

General-purpose processors that are utilized as cores are often incapable of achieving the challenging cost, performance, and power demands of high-performance audio, video, and networking applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a core processor for a particular application. Our goal is to generate a prototype of reconfigurable custom instruction SoC to answer application request using FPGA technology. To give more flexibility to system, we addressed customized core with coarse and finite granularity. In this paper, we provide an overview of a method to identify coarse and finite grain instruction set extensions in application code and integration process in reconfigurable SoC based on NIOSII processor core. 3D synthesis application was proposed as a case study for experimentation.

Automatic C code manipulation and transformation to rapid embedded systems design

Automatic Custom Architecture Generator (ACAgen) is a C-to-Hardware toolset that aims to facilitate and automate the design and development of complex and heterogeneous embedded systems. Framework and algorithms to analyze the initial C code to be exploited in the hardware generation process are needed. Indeed, in the process of Custom Instruction integration within reconfigurable SoC, the initial application C code needs to be automatically updated with the custom instruction opcode. This paper presents the design, and development of an ACAgen Java library able to read, manipulate, and write C code. Its implementation is based on C parsing approach making the SoC design fast and easy. In order to evaluate the usefulness of our ACAgen Java library, we conducted a 3D case study where we applied the new tool to source code of Scalar, Znormal, Projection and other applications. As a result, ACAgen has been able to effectively identify the characteristics of the initial application C code to update it with the hardware components.

Measuring the Quality of IRIS Segmentation for Improved IRIS Recognition Performance

In this paper, we present three versions of an open source software for biometric iris recognition called OSIRIS_V2, OSIRIS_V3, OSIRIS_V4 which correspond to different implementations of J. Daugmans approach. The experimental results on the database ICE2005 show that OSIRIS_V4 is the most reliable on difficult images while OSIRIS_V2 is the fastest. So, we propose a novel strategy for iris recognition using OSIRIS_V2 for good quality images and OSIRIS_V4 when the quality of the segmentation of OSIRIS_V2 is not sufficient to ensure good performance. To this end, we measure the quality of an iris segmentation thanks to a GMM model trained on good quality iris texture and we use a threshold on this quality value to shift between the 2 versions of OSIRIS. We show on ICE2005 database how the choice of this threshold value allows compromising between performance and processing speed of the complete process.

Design of Real Time Multiprocessor System on Chip

Actually, multiprocessor architecture is one of the solutions to fulfill the heavy computational requirements of the new applications running on embedded systems such multimedia and 3D games. The design of such systems pose various problems located at different level: architecture topology, lack of multiprocessor RTOS. Hence, we suggest in this paper a new topology of multiprocessor architecture as well as a generic layer of inter-processor communication which allows the adaptation of the single processor operating systems to multiprocessor architectures. Finally, we round off this article by a comparison between some possible architecture for the design of a system. Those experiments are made through the 3D images synthesis application.

OpenMP-Based Approach for High Level C Loops Synthesis

The complexity of embedded systems design is continuously augmented, due to the increasing quantity of components and distinct functionalities incorporated into a single system. To deal with this situation, abstraction level of projects is incessantly raised. In addition, techniques to accelerate the code production process have appeared. In this context, the automatic code generation is an interesting technique for the embedded systems project. This work presents an automatic VHDL code generation method based on the OpenMP parallel programming specification. In order to synthesize C code for loops into hardware, the authors applied the directives of OpenMP, which specifies portable implementations of shared memory parallel programs. A case study focused on the use of embedded systems for the DCT algorithm is presented in this paper to demonstrate the feasibility of the proposed approach. KeywORdS C for Loops, Java Packages, OpenMP Directives, VHDL

Java-based approach for high level OpenMP loops synthesis

This paper presents an automatic VHDL code generation method based on the OpenMP parallel programming specification. In order to synthesize C code for loops into hardware, we applied the directives of OpenMP, which specifies portable implementations of shared memory parallel programs. The proposed design flow using this method is described and its implementation details are provided. Experimental results show that the generated vhdl code from OpenMP is competitive with optimized code.

Embedded system of the iris segmentation module

Iris Recognition is one of the important biometric recognition systems that identify people based on their eyes and iris. Most modern systems are currently deployed on traditional sequential digital systems, such as a computer. However, modern advancements in reconfigurable hardware, most FPGAs (Field-Programmable Gate Arrays) have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. So that, many authentication applications can be carried out by portable devices. In this paper, we implement the new version C of the iris segmentation [1], which is developed from the Osiris system, in a Cyclone II FPGA DE2_70 FPGA. In the first step, as a software application using Nios II, In the second step, as a hardware-software application using Quartus II and SOPc Builder to accelerate the time processing, after the use of Hardware accelerators. The results show that with a clock speed of 50MHZ from image of 640*480, the gain in the time execution is 768 ms, from the total time needed by the software solution running on the same embedded microprocessor in the architecture.

New version of C code for iris segmentation module

Biometric systems are developed to verily and-or identify persons, for access control, identification systems or border management. They are based on the unique biological characteristics of persons like face, finger, iris, hand, signature, voice. In comparing with other biometric technologies, the iris recognition system has very high recognition accuracy. This system consists of several stages including segmentation stage which is the most important and critical one. In this paper, we present an amiliored version of C code for iris segmentation module. Which is based on the OSIRIS System, coded in C++ language, and had OpenCV library functions. In order to have a new algorithm independent to the OpenCV library, and added the pre-processing module to improve the performance of the OSIRIS system. The system acquires the eyes data from the ICE 2005 data base. This algorithm has a good precision, more than 94. %.

The implementation of basic morphological operations on FPGA using partial reconfiguration

This paper presents a hardware implementation of morphological operations based on dynamic and partial reconfiguration (DPR) technique. This technique allows reconfiguring a part of the FPGA area with different functionalities at runtime. It is a promising solution toincrease performance in the system. Our design allows todesigner to choose the adequate morphological operation (erosion or dilation) according the image constraints. We use xilinx tools and Virtex-5 FPGA board. To evaluate our implementation, we measure the performance in terms of area occupation and time reconfiguration. The results show the implementation of morphological operations on FPGA (Field Programmable Gate Array) using DPR can improve the performance and saving at least 11% of area.