Yasuhiro Yamaji

IMC study on Cu wirebond failures under high humidity conditions

The governing factors of copper wirebond failures under high humidity conditions were experimentally elucidated on the basis of the results of intermetallic compound (IMC) analysis using Scanning Transmission Electron Microscope (STEM). The IMC behavior at the bonding interface under high temperature storage (HTS) test and pressure cooker test (PCT) have been examined and compared. The results of HTS and PCT suggested that the main factor causing the Cu wirebond failures under PCT condition is not a growth of brittle IMC but a corrosion of IMC (Cu9Al4), which is mainly produced during assembly processes and susceptible to corrosion. Result of EPMA mapping for the pad-surfaces on the failure chip indicated that the corrosion is induced by halogen (Cl) in the vicinity of the bonding interface under high humidity condition. The effect of Pd coating and characteristics of mold resin are also discussed on the basis of STEM analysis of the IMC formation and FEM analysis of the thermal stress at the bonding interface.

An 820 pin PGA for ultra large-scale BiCMOS devices

A high-pin-count, high-performance pin grid array (PGA) has been developed for future ASIC devices using half-micron BiCMOS technology and having a maximum usable gate count of 300k. The package has been designed with due consideration of all package functions, electrical, thermal, and mechanical. A surface mount type pin joint was adopted to realize high wiring density on the printed wiring board. The package has 820 pins with a 50-mil pitch and five rows. A highly accurate tape automated bonding (TAB) technology was applied to the die assembly to achieve narrow pitch and high pad count for the bonding between the die and the package. The thermal resistance from the die to the ambient is lower than 1.5 degrees C/W at 1 m/s air flow velocity. The electrical parameters of the package were quantified. The high reliability of the package and surface mount type soldering has been confirmed. >

A novel Wafer level Fan-out Package (WFOP™) applicable to 50um pad pitch interconnects

We present a new embedded package structure and technology for the next generation of WLP, the Wafer level Fun-Out Package; WFOP™. That is one of the face-down mounting styles, which has metal plate like stainless or copper as a base plate of redistributed interconnection layer. The redistributed layer is fabricated with semi-additive method of copper plating. The contact type between the die pads and distributed layer is the lead-type. This structure is hopeful to reduction of fabrication cost by using large scale panel and precise redistribution interconnects control, and its design rule does not depend on the die size. Moreover, WFOP™ has several benefits; applicable to 50µm pad pitch, an excellent thermal characteristics and noise shield by attaching the metal plate. And we obtained the fine results of reliability test. In this paper, we report its package structure, process flow, package characteristics and reliability test results and discussion.