Yoichi Hiruta

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC

A 32-kB cache macro with an experimental reduced instruction set computer (RISC) is realized. A pipelined cache access to realize a cycle time shorter than the cache access time is proposed. A double-word-line architecture combines single-port cells, dual-port cells, and CAM cells into a memory array to improve silicon area efficiency. The cache macro exhibits 9-ns typical clock-to-HIT delay as a result of several circuit techniques, such as a section word-line selector, a dual transfer gate, and 1.0- mu m CMOS technology. It supports multitask operation with logical addressing by a selective clear circuit. The RISC includes a double-word load/store instruction using a 64-b bus to fully utilize the on-chip cache macro. A test scheme allows measurement of the internal signal delay. The test device design is based on the unified design rules scalable through multigenerations of process technologies down to 0.8 mu m. >

Characterization and reduction of simultaneous switching noise for a multilayer package

This paper reports a test chip and an experimental method for characterizing the simultaneous switching noise (SSN) and the noise dependency on the ground pin assignment of a multilayer package. The SSN measurement was executed for various ground pin assignments. The measured results demonstrated that an extra electric current path of the displaced ground pin assignment enhanced the ground bounce due to increasing the effective inductance of package. A balanced pin assignment of the ground pins which suppressed the extra current path in the ground plane had a 20% reduction effect for SSN compared with conventional pin assignments. The extra current path of the ground plane was also verified by an electromagnetic field simulation. The modeling procedure was established for the noise estimation using the inductance value estimated by the field simulation. The circuit simulation resulted in a good agreement with the measured results, and the noise simulation method was applicable for the noise estimation at earlier stage of the package design.<<ETX>>

Simplified and practical estimation of package cracking during reflow soldering process

A simple method has been developed to estimate cracking of plastic packages during reflow soldering process. A criterion for estimating package cracking has been introduced by comparing the mold resin fracture toughness and the maximum value of the stress intensity factor in the package. The criterion equation for package cracking was made to an empirical form. The real-time measurement of package deformation is effective for providing information on the difference of the fracture mode. The difference of the delamination in the package causes the different shape of the deformation curve. The absorption characteristic of the package obeys Ficks law even for thinner packages.<<ETX>>

Flip chip underfill reliability of CSP during IR reflow soldering

Reliability of flip chip CSP (Chip Scale Package) was investigated. The underfill resin for CSP has high saturation content of moisture absorption, compared to a conventional mold resin. The IR reflow test showed no delamination at the underfill interfaces and no package cracking in a flip chip CSP with a ceramic substrate and voidless underfill under the JEDEC LEVEL 1 and 2 conditions. However, it was found out that delamination and package cracking occurred in the IR reflow test under the JEDEC LEVEL 1 when the flip chip CSP has voids in the underfill. The underfill reliability results by IR reflow test confirmed superior reliability of the flip chip CSP with a ceramic substrate and void controlled underfill.

IMC study on Cu wirebond failures under high humidity conditions

The governing factors of copper wirebond failures under high humidity conditions were experimentally elucidated on the basis of the results of intermetallic compound (IMC) analysis using Scanning Transmission Electron Microscope (STEM). The IMC behavior at the bonding interface under high temperature storage (HTS) test and pressure cooker test (PCT) have been examined and compared. The results of HTS and PCT suggested that the main factor causing the Cu wirebond failures under PCT condition is not a growth of brittle IMC but a corrosion of IMC (Cu9Al4), which is mainly produced during assembly processes and susceptible to corrosion. Result of EPMA mapping for the pad-surfaces on the failure chip indicated that the corrosion is induced by halogen (Cl) in the vicinity of the bonding interface under high humidity condition. The effect of Pd coating and characteristics of mold resin are also discussed on the basis of STEM analysis of the IMC formation and FEM analysis of the thermal stress at the bonding interface.

Electrical characterization and modeling of simultaneous switching noise for leadframe packages

Quad-flat packages with a leadframe made of copper (Cu), or alloy 42 are widely used for CMOS digital applications. As the clock speed of CMOS VLSIs increases, the package inductance is considered to be a limiting factor for their performance. To investigate the relationship between package inductance and switching noise, three types of leadframe materials, Cu, alloy 42, and Ag-plated alloy 42 were prepared. Frequency-dependent properties of leadframe materials were measured up to a high frequency range. Then, extensive experiments were executed by using a CMOS noise generating chip to measure how leadframe materials influence switching noise in conjunction with output buffer characteristics. The alloy 42 leadframe is believed to be unsuitable for high-speed CMOS applications because of its high permeability of ferromagnetics. However, it has been proved that the large inductance difference at lower frequencies does not greatly affect switching noise at practical operating frequencies. A modeling approach for leadframe packages was executed by taking mutual inductances into consideration and by using the measured values of inductances and resistance.

Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

Eutectic solder flip chip fabrication technology, through bumping to assembly process, has been developed. In bumping process, electroplating method and thick photo resist process could form eutectic solder bumps whose uniformity of height are less than 10% within wafer. Eutectic solder flip chip assembly process, which includes bonding, cleaning and underfilling, has been also developed. Bonding process of eutectic solder indicates good self-alignment. The excellent rosin cleaning was achieved by the ultrasonic cleaning process with Techno Care. In underfilling process, the underfill resin which can be applied to small stand-off have been chosen. Reliability tests for CSP and flip chip interconnection were carried out and confirmed the good reliability of fabrication process using eutectic solder flip chip technology.

Thermal management of embedded device package

Higher performance and miniaturization are current trends of electronic equipment, with many devices mounted with a high density on a printed board. The heat density of devices is also increasing. Heat causes various problems in devices, for example, it reduces their processing speed and causes malfunctions. Controlling the thermal resistance of packages is essential for their development. The thermal resistance can be estimated by numerical analysis and accurate estimation is important. This paper describes thermal management by thermal analysis of the Wide Strip-Fan Out package (WFOP™) produced by J-Devices, which is an embedded device package using a metal plate as a base plate. Samples with test element groups were fabricated and the correlation between measurement and simulation results was examined. The accuracy of simulation was improved by reviewing both the measurement data and the simulation models. Finally low-thermal-resistance packages were realized using the method of simulation.

Effectiveness of Thin‐film Barrier Metals for Eutectic Solder Bumps

This paper describes effective thin‐film structure barrier metals for use as eutectic solder bumps. Shear strength and bump interconnection resistance were evaluated. The mutual diffusion in metals was investigated. Barrier metal structures —Cu/Ti,Ni/Ti and Cu/Cr—were evaluated after ageing. The Ni/Ti structure has good reliability according to ageing test results. Pd is used for improvement of solder wettability and as an oxidisation barrier. Consequently, it was concluded that a thin‐film Pd/Ni/ Ti barrier metal is suitable for use as eutectic solder bumps. The broken interfaces of the solder bumps were analysed by scanning auger electron spectrometry. In the thin‐film Cu/Ti structure, decrease in the shear strength is caused by three mechanisms, as determined from the broken interface analysis. The three mechanisms are mixed metal formation, Ti oxidisation and diffusion between barrier metals and Al. Furthermore, TCT and PCT were carried out on these eutectic solder bumps to confirm the interconnection...

Advanced packaging technologies supporting new semiconductor application

Packaging interconnect technologies which connect between semiconductor and interposer have been developed by changing with wire bonding, flip-chip and re-distribution layer (RDL). The latest interconnect technologies are introduced.