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Dive into the research topics where Yasuhito Yoshimizu is active.

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Featured researches published by Yasuhito Yoshimizu.


international interconnect technology conference | 2007

Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric

Takeshi Watanabe; H. Nasu; Gaku Minamihaba; N. Kurashima; A. Gawase; Miyoko Shimada; Yasuhito Yoshimizu; Yoshihiro Uozumi; Hideki Shibata

Self-formed barrier technology using copper (Cu) manganese (Mn) alloy seed was applied for Cu dual-damascene interconnect with porous-SiOC/porous-PAr (k=2.3) hybrid dielectric for the first time. More than 90% yield for wiring and via-chain was obtained. 70% reduction in via resistance was confirmed compared with the conventional process. To estimate the moisture resistance property of self-formed barrier, via resistance change was measured with dummy density pattern. As the result, it was found that the resistance change ratio of via for self-formed barrier does not depend on the dummy density, probably due to the high moisture resistance property of self-formed oxide barrier. In addition, outgas at high temperature is found to be essential to form self-formed barrier for porous dielectric.


international interconnect technology conference | 2007

Development of an Eco-friendly Copper Interconnect Cleaning Process

Yoshihiro Uozumi; Takahito Nakajima; Tsuyoshi Matsumura; Yasuhito Yoshimizu; Hiroshi Tomita

This paper reports the development of an eco-friendly, low-cost and clean wet cleaning process in forming copper interconnections, especially on a copper surface at the bottom of the via. From analysis and electrical data, the components of post-etch residues are mainly formed by copper fluorides, copper oxides and silicon oxides. Therefore, diluted inorganic acid solutions are used to remove these polymers and a diluted amine solution is used to stabilize the copper surface after cleaning. These chemicals are treated by an effluent treatment facility, and are very cheap and clean. In the results of post-cleaning, the analysis data shows that the residues are removed, and the electrical data such as via chain yield, electro migration, etc., shows good performance.


international symposium on semiconductor manufacturing | 2007

Fine edge and bevel film stripping process by novel wet cleaning tool beyond 45nm node

Yoshihiro Ogawa; Hidenobu Nagashima; Yasuhito Yoshimizu; Hiroshi Tomita; Takuya Kishimoto; Katsuhiko Miya; Akira Izumi

In this paper, we indicate the difficulty of high-k film stripping of edge cut area using conventional bevel and backside etching tool and propose a fine edge cut control process using a novel bevel and backside etching tool with edge dispense nozzles.


Archive | 2009

CLEANING APPARATUS FOR SEMICONDUCTOR WAFER AND CLEANING METHOD FOR SEMICONDUCTOR WAFER

Minako Inukai; Hiroshi Tomita; Kaori Umezawa; Yasuhito Yoshimizu; Linan Ji


Archive | 2010

Semiconductor substrate cleaning method

Hiroshi Tomita; Hisashi Okuchi; Minato Inukai; Hidekazu Hayashi; Yasuhito Yoshimizu


Archive | 2010

CLEANING METHOD FOR SEMICONDUCTOR WAFER

Hiroshi Tomita; Hidekazu Hayashi; Minako Inukai; Yasuhito Yoshimizu; Kaori Umezawa


Archive | 2012

Stacked multiple cell nonvolatile memory device

Yasuhito Yoshimizu; Fumiki Aiso; Atsushi Fukumoto; Takashi Nakao


Archive | 2012

METHOD FOR FORMING INTERCONNECTION PATTERN AND SEMICONDUCTOR DEVICE

Yasuhito Yoshimizu; Satoshi Wakatsuki; Hisashi Okuchi; Atsuko Sakata; Hiroshi Tomita


Archive | 2009

Cleaning apparatus for semiconductor wafer

Minako Inukai; Hiroshi Tomita; Kaori Umezawa; Yasuhito Yoshimizu; Linan Ji


Archive | 2017

A THREE-DIMENSIONAL MEMORY DEVICE

Yasuhito Yoshimizu; Akifumi Gawase; Yuya Akeboshi

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Akira Izumi

Kyushu Institute of Technology

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