Yasunari Shiba

Behavior of Misfit Dislocations in GaAs Epilayers Grown on Si at Low Temperature by Molecular Beam Epitaxy

The behavior of misfit dislocations in GaAs buffer layers grown on Si was investigated by the measurement of stresses using optical interferometry and X-ray diffraction. The buffer layers grown at 250°C with various thicknesses (0.05~0.20 µm) were annealed at various temperatures (400~600°C). The overlayers were grown at 300°C. With increasing annealing temperature or thickness, the stresses changed from compressive to tensile. The stress-free GaAs/Si wafer was produced with a 0.10-µm-thick buffer layer annealed at 500°C. These results indicate that in low-temperature growth, it is important to optimize both the annealing temperature and the thickness of the buffer layer. In addition, the asymmetric stresses were observed between [011] and [01]. This asymmetry was caused by the difference in dislocation velocities or nucleation energies between α- and β-dislocations.

Threading dislocation reduction in GaAs on Si with a single InGaAs intermediate layer

The threading dislocation reduction behavior upon insertion of a single thick InGaAs intermediate layer into the GaAs heteroepitaxial layers on Si has been investigated. In the X-ray diffraction, with increasing InGaAs thickness below 0.5 µ m, the full width at half-maximum (FWHM) of the GaAs overlayer decreases even if the InGaAs thickness is beyond the critical layer thickness. In the cross-sectional transmission electron microscopy (TEM) observations, it has been found that sufficient misfit dislocations are introduced and that the threading dislocation density decreases at the GaAs/InGaAs interfaces in samples with InGaAs thicker than 0.1 µ m. The analysis based on the mechanical equilibrium theory shows that misfit dislocation formation at the interfaces plays an important role in reducing the threading dislocation density. The InGaAs intermediate layer is required to be thick enough to form misfit dislocations at the interfaces with relaxation of strain in the intermediate layer.

MOCVD growth of GaAs on Si using (Al,In) GaAs/GaAs buffer layer

Abstract GaAs was grown on Si using an (Al,In)GaAs/GaAs buffer layer. The etch pit density (EPD) revealed by molten KOH could be reduced by adding Al x Ga 1− x As or In x Ga 1− x As to the GaAs buffer layer, depending on the composition ( x ); the lowest EPD, 4×10 6 cm -2 was obtained when x was 0.3 in Al x Ga 1− x As. To understand the results, the initial growth stage of GaAs on Si was investigated by scanning electron microscopy. GaAs growth using an Al 0.3 Ga 0.7 As layer produced small islands at a sufficiently high density that the islands coalesced, unlike those without the layer. The dependence of EPD and island density on the composition ( x ) were almost the same. This result indicates that improvement of the quality of the GaAs layer is related to the coalescence of the GaAs island at an early stage of the growth of GaAs on Si.

Dynamical Formation Process of Pure Edge Misfit Dislocations at GaAs/Si Interfaces in Post-Annealing

We investigate the dynamical formation process of pure edge misfit dislocations (90° type) in GaAs/Si(100) (3° off toward [011]). The cross sections at the interfaces of GaAs/Si annealed at various temperatures (300–600° C) are observed by high-resolution transmission electron microscopy. The pure edge dislocation is formed by the reaction of two mixed dislocations (60° type) at the interface, and is not introduced directly from the epilayer surface. To explain the experimental results, we present a new formation process of pure edge dislocations: (1) glide from the epilayer surface, (2) climb along the interface and (3) reaction. In this process, the climb motion along the interface is most important. In addition, the difference in the ratio of pure edge dislocations to the total dislocations was observed between stepped and flat directions of the Si substrate. This asymmetry may be caused by the difference in climb velocities along the interface. The Si surface steps probably enhance this climb motion.

The Effects of AsH3 Preflow Conditions at Low Temperature on the Morphology of GaAs Buffer Layers for GaAs/Si Grown by Metalorganic Chemical Vapor Deposition

In the two-step growth of GaAs on Si, the effects of AsH3 preflow conditions (preflow time and preflow rate) at a low temperature (450°C) on the morphology of GaAs buffer layers (GaAs islands) have been investigated with scanning electron microscopy. As the preflow time or preflow rate was increased, the islands were aligned parallel to the step edges of the misoriented Si surface, and Si surface coverage was increased. These results indicate that the sufficient AsH3 preflow to the Si surface at low temperatures forms both multilayer steps on the Si surface for GaAs island nucleation and a stable GaAs/Si interface.

Si substrate preparation for GaAs/Si by metalorganic chemical vapor deposition

Abstract The effects of pre-growth treatments on Si substrates on the quality of GaAs epilayer have been studied by MOCVD. GaAs layers were grown on Si substrates tilted 2° toward the [011] direction using a two step growth method. All GaAs epilayers grown were single domain, although two crystallographic orientations with respect to the tilted direction were detected depending on the pre-growth and/or growth conditions. Crystallographic orientation is interchanged depending on the temperature and time of the AsH 3 preflow and the V/III ratio. Furthermore, the crystallinity of GaAs on Si is poor for an AsH 3 preflow temperature above 650°C, in comparison with those below 650°C. The crystallinity of GaAs on Si is independent of the crystallographic orientation.

AsH_3 Pre-Exposure Conditions for GaAs Epitaxial Growth on Si by Melalorganic Chemical Vapor Deposition

The effects of AsH3 pre-exposure at high temperature on the crystalline quality of GaAs layer grown on Si have been studied using X-ray diffraction. The full width at half-maximum (FWHM) of the (400) reflection from the GaAs layer was affected by the pressure; at 100O°C, the sample with the AsH3 pre-exposure at 76 Torr shows narrower FWHM than that with the pre-exposure at 760 Torr. Both samples are analyzed by SIMS. The concentration profile of As and Si around the interface in the sample with lower pressure is sharper than that in the sample with higher pressure.

Metal Organic Chemical Vapor Deposition Growth of GaAs on Si Using GaAs Buffer Layer Grown by an Alternate Gas Flow of Source Materials

We tried the atomic layer epitaxy (ALE) growth of GaAs initial layer in a two-step growth of GaAs on Si by a conventional metal organic chemical vapor deposition (MOCVD) system. The etch pit density of GaAs overlayer became smaller than that without this approach. The cross sectional transmission electron microscope (TEM) of this sample indicated that the improvement of crystalline quality of GaAs overlayer was attributed to the smooth interface structure of GaAs/Si due to the layer by layer growth of the buffer layer.

Raman scattering study on the first step growth of GaAs on Si grown by MOCVD

Abstract Raman scattering measurements were done for the first step growth layers of GaAs on Si grown at 450°C by metalorganic chemical vapor deposition to study their crystalline quality. The longitudinal optical (LO) phonon was observed in the layers grown at 760 Torr, while no significant peak was observed in those grown at 76 Torr. The poor crystalline quality of the layers grown at 76 Torr was caused by the nucleation of a large number of small islands.

X-ray topographic observation of subsurface line defects in GaAs on Si substrate

Defects in GaAs epilayers on Si substrates grown by MOCVD have been studied. Subsurface defects in both epilayers and substrates generated during the device fabrication process were observed, using X-ray double crystal topography. In order to clarify the defect formation mechanism, the influence of Si preheating prior to epitaxial growth on the defect formation was also examined. It was found that the defects in the GaAs epilayer occur simultaneously with defect formation in Si substrates and the defect density decreased with the lowering of the preheating temperature of the Si substrate in AsH3 gas flow. These defects extended along the [011] or [011] direction with respect to substrate misorientation in the [011] direction and were revealed as images with peculiar contrasts in X-ray topographs. The images can be explained in terms of lattice plane distortion caused by crack formation. These results indicate that microcracks first form at the epilayer-substrate interface and then propagate in both the GaAs epilayer and the Si substrate in the slip mode.