Koyu Asai

Local Bonding Structure of High-Stress Silicon Nitride Film Modified by UV Curing for Strained Silicon Technology beyond 45 nm Node SoC Devices

Silicon nitride films (p-SiN) with different high stresses were formed by changing the monosilane-to-ammonia source gas ratio, RF power, and deposition temperature in a conventional plasma-enhanced chemical vapor deposition (PECVD). PECVD was used to deposit p-SiN films with high-stresses because it can flexibly change the stress of the film to be formed from tensile to compressive direction. The formed films were analyzed by Fourier transform-infrared spectroscopy (FT-IR), X-ray photoelectron spectroscopy (XPS), nanoindentation, and positron-beam annihilation to obtain data on local bonding structure, mechanical properties and the behavior of vacancies in the p-SiN films. In this study, to clarify the local bonding structure of high stress SiN films, we investigated p-SiN films with and without ultraviolet (UV) curing that is effective in tensile stress. It has been confirmed that total hydrogen (Si–H+N–H) concentration decreases with increasing film stress of p-SiN films. It has been found that UV curing promotes Si–N–Si crosslinking due to dehydrogenization, leading to the formation of a stoichiometric silicon nitride, Si3N4, network structure, and the vacancies in the p-SiN films shrink during UV curing. Finally, we proposed a structural model for the local bonding arrangement in p-SiN films with UV curing.

Advanced Air Gap Process for Multi-Level-Cell Flash Memories Reducing Threshold Voltage Interference and Realizing High Reliability

As the cell size of flash memories is scaled down, the reading error due to threshold voltage (Vth) interference has become a more serious problem, particularly in the case of multi-level-cell (MLC) flash memories, it is necessary for the Vth distribution to be narrower than that of the single-level-cell (SLC). In this work, we propose an advanced air gap structure and process to reduce the interference due to the capacitance between floating gate and floating gate. By applying an air gap between neighboring floating gates as a lowest-dielectric-constant material, we can suppress Vth interference markedly. In addition, we clarified the correlation between the air gap forming process and the memory cell reliability. Hydrogen included in the SiO2 film, which is deposited by plasma-enhanced chemical vapor deposition (CVD) during air gap formation causes the degradation of memory cell endurance and the de-trapping characteristics. We were able to achieve a high-reliability memory cell by reducing the hydrogen concentration in the SiO2 by optimizing the deposition process for air gap formation.

Lattice relaxation of GaAs islands grown on Si(100) substrate

Initial stage of lattice relaxation of GaAs islands grown on Si(100) substrate were investigated by combination of reflection high-energy electron diffraction and molecular beam epitaxy. In addition to the lattice constants in horizontal direction (a∥) to the substrate surface, we first measured directly those in vertical one (a⊥). At the beginning of the growth, the rapid increase of a∥ and the larger Poisson’s ratios than that of bulk were observed. Atomic bond flexibility and extension induced by surface effects might cause this rapid increase of a∥ and large Poisson’s ratios.

Behavior of Misfit Dislocations in GaAs Epilayers Grown on Si at Low Temperature by Molecular Beam Epitaxy

The behavior of misfit dislocations in GaAs buffer layers grown on Si was investigated by the measurement of stresses using optical interferometry and X-ray diffraction. The buffer layers grown at 250°C with various thicknesses (0.05~0.20 µm) were annealed at various temperatures (400~600°C). The overlayers were grown at 300°C. With increasing annealing temperature or thickness, the stresses changed from compressive to tensile. The stress-free GaAs/Si wafer was produced with a 0.10-µm-thick buffer layer annealed at 500°C. These results indicate that in low-temperature growth, it is important to optimize both the annealing temperature and the thickness of the buffer layer. In addition, the asymmetric stresses were observed between [011] and [01]. This asymmetry was caused by the difference in dislocation velocities or nucleation energies between α- and β-dislocations.

Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique

A novel low-leakage-current nickel self-aligned-silicide (SALICIDE) process in n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on Si(110) substrates is reported. Anomalous nickel silicide encroachment in the direction in nMOSFETs on Si(110) substrates is found for the first time. This encroachment causes anomalous off-state leakage current (Ioff) in nMOSFETs on Si(110) substrates. In particular, in the case of the channel on Si(110) substrates, Ni atoms easily diffuse in the direction, and nickel silicide preferentially grows in the direction. As a result, anomalous leakage current between the drain and the source occurs, and the leakage current seriously degrades transistor performance. In order to overcome these problems, we propose a method of suppressing anomalous Ioff on Si(110) substrates by Si+ ion-implantation technique prior to the nickel SALICIDE process. This method is effective for suppressing the encroachment of nickel silicide and realizing low-leakage complementary metal–oxide–semiconductor (CMOS) devices on Si(110) substrates.

Highly Reliable Cu Interconnect Using Low-Hydrogen Silicon Nitride Film Deposited at Low Temperature as Cu-Diffusion Barrier

We demonstrated highly reliable Cu interconnects using a high-quality silicon nitride film grown at temperatures below 300 °C. The low-temperature silicon nitride (LT-SiN) film, which was used as a Cu-diffusion barrier layer and a final passivation layer, was deposited at 275 °C by plasma-enhanced chemical vapor deposition at a low SiH4 flow ratio. The low SiH4 flow ratio was due to the use of a highly dilute nitrogen flow, leading to the generation of many nitrogen radicals or ions in the plasma. These radicals or ions might reduce the hydrogen concentration and defect density of the film. As a result, a stoichiometric silicon nitride (Si3N4) film with a low hydrogen concentration was successfully obtained. By applying this LT-SiN film in 130-nm-node Cu interconnects for magnetoresistive random access memory, highly reliable via-hole electromigration (Via-EM) and line-to-line time-dependent dielectric breakdown (TDDB) characteristics were obtained.

Threading dislocation reduction in GaAs on Si with a single InGaAs intermediate layer

The threading dislocation reduction behavior upon insertion of a single thick InGaAs intermediate layer into the GaAs heteroepitaxial layers on Si has been investigated. In the X-ray diffraction, with increasing InGaAs thickness below 0.5 µ m, the full width at half-maximum (FWHM) of the GaAs overlayer decreases even if the InGaAs thickness is beyond the critical layer thickness. In the cross-sectional transmission electron microscopy (TEM) observations, it has been found that sufficient misfit dislocations are introduced and that the threading dislocation density decreases at the GaAs/InGaAs interfaces in samples with InGaAs thicker than 0.1 µ m. The analysis based on the mechanical equilibrium theory shows that misfit dislocation formation at the interfaces plays an important role in reducing the threading dislocation density. The InGaAs intermediate layer is required to be thick enough to form misfit dislocations at the interfaces with relaxation of strain in the intermediate layer.

AsH3 preflow effects on initial stages of GaAs grown on Si by metalorganic chemical vapor deposition

The effect of AsH3 preflow on initial stages of GaAs grown on Si was studied by transmission electron microscopy. As the temperature of AsH3 preflow was increased, the surface of the Si substrate became rougher: At 1000 °C, many threading dislocations originating at the rough surface were observed in the GaAs layer. In contrast, at low temperature, 450 °C, the Si surface became smooth and the dislocations were reduced. Furthermore, the Si surface was still smooth after long AsH3 preflow at 450 °C. The roughness of the Si surface is attributed to the supply of As atoms to the Si surface at high temperature.

Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28 nm Node and Beyond

With continuous shrinkage of advanced ultralarge scale integrations (ULSI), the impact of line resistance on the devices has become more and more important. In order to achieve low resistance and high reliability of Cu interconnects, we have applied a thin Ti-based self-formed barrier layer using Cu–Ti alloy seed to 45 nm node dual-damascene interconnects and evaluated its performance. The microstructure analysis by transmission electron microscope and energy dispersive X-ray fluorescence spectrometer has revealed that 2-nm-thick Ti-based barrier layer is self-formed at the interface between Cu and low-k dielectrics. The line resistance and via resistance decrease significantly, compared with those of conventional Ta/TaN barrier system. The stress migration performance is also drastically improved using self-formed barrier process. These results suggest Ti-based self-formed barrier process is one of the most promising candidates for advanced Cu interconnects.

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

We have investigated the characteristics of silicon oxide films deposited by plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) as offset spacer films of high-k/metal gate stacks. From the results of bonding structure analysis, the silicon oxide film deposited by PEALD has been found to be composed of a Si–O bond network of the stoichiometric silicon oxide film. On the other hand, the silicon oxide film deposited by PECVD is considered to contain suboxide bond structures. From the results of physical and mechanical evaluations, the silicon oxide film deposited by PEALD exhibits a lower wet etch rate, a higher film density, a lower dielectric constant, a smaller amount of water in the film, and a higher elastic modulus than that deposited by PECVD. PEALD showed excellent thickness controllability. From these results, the silicon oxide film deposited by PEALD has higher quality and is more suitable for use as an offset spacer than that deposited by PECVD. X-ray photoelectron spectroscopy showed that the surface oxidation of a titanium nitride film, which is used as a metal gate electrode, during PEALD can be suppressed by using a lower PEALD temperature. Finally, we have demonstrated that the drain current of a high-k/metal gate transistor with a silicon oxide offset spacer deposited by PEALD is markedly increased, compared with that with a high-temperature-deposited silicon oxide offset spacer.