Yasunobu Kosa

Method for forming a lightly-doped drain (LDD) structure in a semiconductor device

Dram with a vertical capacitor and transistor

Semiconductor device having a static-random-access memory cell

Vertical field-effect transistor and a semiconductor memory cell having the transistor

Field effect transistor having control and current electrodes positioned at a planar elevated surface and method of formation

Structure for shielding conductors

Methods of forming a vertical field-effect transistor and a semiconductor memory cell

Process for forming a structure which electrically shields conductors

Method for forming a buried contact

Static RAM cell with soft error immunity