John R. Yeargain

A fully complementary BiCMOS technology for sub-half-micrometer microprocessor applications

A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5- mu m microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n/sup +//p/sup +/) gate CMOS process flow. Using a collector pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi/sub 2/ Schottky-barrier diode are also available for circuit applications. Stacking of the tungsten-plug contacts and vias are allowed in the multilevel metallization module. Comparing the CMOS and BiCMOS implementation of a 68030 critical path, 40% speed improvement at 3.3-V Vcc and a CMOS/BiCMOS crossover at 2.2 V have been obtained for this logic BiCMOS technology. >

A 0.4 micron fully complementary BiCMOS technology for advanced logic and microprocessor applications

A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5 mu m logic and microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n/sup +//p/sup +/) gate CMOS process flow. Using a pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi/sub 2/ Schottky barrier diode devices formed during the titanium self-aligned silicide process are available for various circuit applications. Stacking of the tungsten-plug contacts and vias is allowed in the multilevel metallization module. A process window analysis has also been performed to derive the optimal device design targets. Compared with the CMOS counterpart, approximately 40% speed improvement (at 3.3 V V/sub cc/) in a 68030 critical path has been demonstrated using this logic BiCMOS technology.<<ETX>>

A high density floating-gate EEPROM cell

An electrically erasable PROM cell is described which is implemented in a N-channel double polysilicon gate process. The cell is composed of a double poly floating-gate memory device and a select transistor. Electrical programming and erasure of the floating-gate transistor is achieved by field emission of electrons through a thin oxide. The memory transistor exhibits an endurance of greater than 105program-erase cycles with extrapolated data retention in excess of ten years. The cell has been used to develop a 32K EEPROM memory chip which operates from a single +5 volt supply during read. Typical access time is 100 ns. An extra +21 volt DC supply is used to program or erase the device in less than 10 ms.

Study of BiCMOS logic gate configurations for improved low-voltage performance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10 degrees C and sub-2 V at 110 degrees C. >

Low-defect-density and high-reliability FETMOS EEPROM's fabricated using furnace N/sub 2/O oxynitridation

The superior characteristics of floating-gate electron tunneling MOS (FETMOS) EEPROMs fabricated using a furnace N/sub 2/O oxynitridation process are described. These devices exhibited about eight times better endurance and good data retention characteristics while maintaining defect density comparable to that of the control thermal oxide devices. These devices also showed very good thickness uniformity across the wafer and wafer-to-wafer.<<ETX>>

An advanced high voltage CMOS process for custom logic circuits with embedded EEPROM

An advanced high-voltage CMOS process has been developed for custom products with on-chip electrically erasable programmable read-only memory (EEPROM). The minimum feature size is 1.2 mu m. Process adjustments to achieve >18-V high-voltage operation are explained in detail. Performance of short-channel transistors with L/sub eff/<1.0 mu m is also described. The Motorola FETMOS EEPROM cell characteristics and reliability are discussed. Microprocessor chips with up to 68K bits of EEPROM have been fabricated using this process.<<ETX>>

A dual-poly (n + /p + ) gate, Ti-salicide, double-metal technology for submicron CMOS ASIC and logic applications

The process architecture and device characteristics of a submicrometer CMOS n+/p+ poly gate, Ti-salicide, double-metal technology are described. Tradeoffs among circuit shrinkability, device gain, and hot-carrier-injection susceptibility are discussed. This technology has been successfully implemented in a 0.8-μm unified-design-rule high-performance high-end MPU product

A novel 0.5- mu m n/sup +/-p/sup +/ poly-gated salicide CMOS process

A novel salicided twin-tub 0.5- mu m CMOS process using germanium implantation is presented. n/sup +/ and p/sup +/ dopants are implanted after salicide formation to fabricate devices with low junction leakage and low silicide-to-diffusion contact resistance. Germanium implantation prior to silicide formation is used to control short-channel transistor characteristics. A significant reduction in the lateral n/sup -/ and p/sup -/ diffusion is observed for germanium-implanted LDD (lightly doped drain) MOSFETs, resulting in minimized overlap capacitance as well as improved short-channel behavior. >

A high performance CMOS technology for 256K/1MB EPROMs

A technology has been developed which integrates new pro cesses necessary to implement high performance and reliable CMOS EPROMS. This technology consists of a single 250 A first poly transistor with double diffused source and drains utilized both for high voltage circuitry (Leff= 2.2 um) as well as peripheral circuits (Leff= 1.2 um). Furthermore, a thin oxide-nitride -oxide (ONO) interpoly dielectric for reliable floating gate performance is incorporated. Good dielectric breakdown, defect density, and charge retention characteristics are obtained. Write characteristics as well as softwrite endurance have been measured to be compatible with current high density EPROM designs.

Oxide charge trapping and HCI susceptibility of a submicron CMOS dual-poly (N/sup +//P/sup +/) gate technology

Gate-oxide charge trapping and hot-carrier injection (HCI) susceptibility of a submicrometer CMOS dual-poly (n/sup +//p/sup +/) gate, Ti-salicide, double-metal technology are discussed. The Si-SiO/sub 2/ interface property is believed to be modified by the p/sup +/ poly gate process, possibly due to boron penetration from the p/sup +/ polysilicon into the gate oxide. This accounts for the observed reduction in hole trapping during constant-current stress of the p/sup +/ poly gate capacitors and the large critical energy for interface trap generation during HCI stress of the p/sup +/ poly gate transistors. A general empirical relationship between the HCI power law parameters A (the precoefficient) and n (the power index) was obtained for both n-channel p-channel devices to describe the stress-time dependent degradation. Using the derived MOSFET lifetime, the limiting device type for this submicrometer CMOS dual-poly gate technology has also been determined. >