Yasunori Miyahara

Design of a 300-mV 2.4-GHz Receiver Using Transformer-Coupled Techniques

This paper presents a 1.6-mW 2.4-GHz receiver that operates from a single supply of 300 mV allowing direct powering from various energy harvesting sources. We extensively utilize transformer coupling between stages to reduce headroom requirements. We forward-bias bulk-source junctions to lower threshold voltages where appropriate. A single-ended 2.4 GHz RF input is amplified and converted to a differential signal before down-converting to a low IF of 1 to 10 MHz. A chain of IF amplifiers and narrowband filters are interleaved to perform programmable channel selection. The chip is fabricated in a 65-nm CMOS process. The receiver achieves -91.5-dBm sensitivity for a BER of 10e-3.

A 1.6mW 300mV-supply 2.4GHz receiver with −94dBm sensitivity for energy-harvesting applications

The goal of this work was to design a 2.4GHz receiver that operates with a supply voltage of 300mV, allowing direct powering from various energy-harvesting sources. Our target application is body-worn wireless devices requiring high datarates (wirelessly tethered hearing aids, for example). This application allows access to multiple energy-harvesting power sources, like photovoltaic and thermoelectric power harvested from body heat.

Next-generation wireless technologies trends for ultra low energy

Mobile communication technology has been improving the connection speed every year. In addition, the wireless communication LSI improves not only speed but also the reliability and functionality due to market requirements. As a result, the power of consumption of the wireless RF chip LSI has been much bloated. Currently, Panasonic is interested in two categories of technology in the new market area. One is the ultra-low power radio technology with several kbps which requires more than decade operation by a single coin battery. Another is the ultra-high-speed radio technology for data transfer. Both common wireless technologies can extremely reduce power consumption in terms of the parameter of energy expense over 1-bit (pJ/bit technology). In this talk, we introduce the technology of the low power radio system ever developed for a cellular phone. The digital RF architecture with polar transmitter system can improve the power amplifier efficiency. Then we introduce the ultra-low power wireless core technologies for RF, including the standardizations. Simple OOK signal modulation in wireless system can extremely reduce the total power consumption in RF. The low power system and circuit technique are introduced. These ultra-low-power radios are used for the smart grid home network based on the IEEE802.15.4g or body area network based on IEEE802.15.6 for future products. Finally, we explain Giga-bit wireless data communication where 60 GHz-band is one of the most attractive frequency resources, since 60 GHz band has already been allocated as unlicensed band with more than 7 GHz bandwidth in most of countries,. IEEE802.15.3c specification has been developed as the wireless personal area network (WPAN) standard above 1-Gbps in 2009. Other standardization bodies, such as the Wireless Gigabit Alliance and the IEEE802.11ad are also being developed for the wireless local area network (WLAN) toward 2012. All standards are targeting short range wireless connectivity among personal computers, audio-video equipments and mobile devices (e.g. smart phone or digital still camera) for uncompressed high-definition (HD) video stream and/or “sync and go” file transfer applications. In order to realize gigabit wireless connectivity for mobile, low power consumption less than 1 W with more than1 Gbps (less than 1pJ/bit) is required. Achieving such a low power radio at 60 GHz including the high-speed baseband is challenging. Using a CMOS technology is a promising approach to realize single chip solution with less than 1pJ/bit.

A Novel Parasitic-Aware Synthesis and Verification Flow for RFIC Design

The design of radio-frequency integrated circuits (RFICs) is highly sensitive to layout parasitics. In conventional methodologies, the layout parasitics are known only after the layout is complete and the schematic is resized to compensate for these parasitics. The drawback of such a methodology is that the convergence of this design iteration remains unpredictable. This paper proposes a novel synthesis and verification flow for RFIC designs. The design flow is composed of three stages: circuit sizing with floorplan, performance-aware floorplan refinement, and full-wave electromagnetic (EM) extraction. Layout parasitics are considered throughout the design flow in the proposed methodology. As a result, parasitic closure can be achieved quickly and design iterations may not be required. As an example, the proposed design flow is applied to a cross-coupled inductance-capacitance (LC) VCO. Demonstrating the efficiency of the proposed flow for RFIC designs, it required only two weeks to meet all the design specifications with no iterations