Shunsuke Hirano

A fully integrated PLL frequency synthesizer LSI for mobile communication system

A fully integrated phase locked loop (PLL) frequency synthesizer LSI has been developed. This newly developed fractional-N type PLL LSI consists of an on-chip loop filter and a voltage controlled oscillator (VCO) with an on-chip resonator circuit. This VCO has a band-switching tuning circuit using MOS capacitors and an analog tuning circuit using PN varactor diodes. Both these tuning circuits are controlled automatically without external adjustment. The phase noise of the VCO at 2.2 GHz is -92.5 dBc/Hz at 50 kHz offset, while the frequency switching time is 170 /spl mu/s.

VCO gain nonlinearity calibration with frequency offset/drift compensation for 3G/GSM/EDGE polar modulation transmitter

In recent 3G cellular handset, small-sized RF is strongly demanded. Polar modulation is one of the candidates to eliminate peripheral RF components. To apply polar modulation for wideband application, high linearity of phase modulator is required. In this paper, VCO gain nonlinearity calibration for phase modulator is proposed. The proposed procedure can calibrate the nonlinearity including frequency offset and frequency drift, which have an impact on EVM performances. Simulation and measurement results show the proposal can achieve excellent EVM of 5.8%.

An RFIC within a direct open-loop polar multimode transmitter for UMTS/EDGE/GSM

An RFIC within a direct open-loop polar multimode transmitter that supports UMTS, GSM, and EDGE is shown in 0.18 mum CMOS. Design details, and chipset system application are explained. The chip architecture applies phase accurate FLL two-point modulator with SigmaDelta feedback control for AM-PM corrected wideband phase modulation to an LC VCO, and AM-AM corrected envelope drive of multi-stage saturated PA. IC measurement results and chip-set system performance are presented.