Yasuo Kanetake
Rohm
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Publication
Featured researches published by Yasuo Kanetake.
2017 IEEE International Workshop On Integrated Power Packaging (IWIPP) | 2017
Takaaki Ibuchi; Eisuke Masuda; Tsuyoshi Funaki; Hirotaka Otake; Tatsuya Miyazaki; Yasuo Kanetake; Takashi Nakamura
This report focuses the current distribution in a module identifiedwith magnetic near-field intensity for optimizing layout and packaging design of silicon carbide (SiC) power module. This measurement methodology can visualize the practical current distribution on a wiring pattern in a module and can estimate the effect of snubber capacitor in a DC-link of half-bridge to suppress the voltage overshoot and ringing oscillation.
international symposium on electromagnetic compatibility | 2017
Eisuke Masuda; Takaaki Ibuchi; Tsuyoshi Funaki; Hirotaka Otake; Tatsuya Miyazaki; Yasuo Kanetake; Takashi Nakamura
The fast switching operation of wide-bandgap power semiconductor devices deteriorates the Electromagnetic interference (EMI) noise characteristics of a power converter. The parasitic inductance in a power module is one cause of noise generator. This paper calculates parasitic inductance in a wiring pattern of module with Partial Element Equivalent Circuit (PEEC) method, and evaluates the current distribution in a module by magnetic near-field intensity measurement to discuss the suitable wiring pattern design for intelligent silicon carbide (SiC) power module.
Archive | 1994
Yasuo Kanetake
Archive | 2004
Yasuo Kanetake
Archive | 1994
Miki Hasegawa; Yasuo Kanetake
Archive | 1997
Tomohiro Tomiyasu; Yasuo Kanetake
Archive | 1996
Tomohiro Tomiyasu; Yasuo Kanetake
Archive | 1994
Yasuo Kanetake
Archive | 1997
Tomohiro Tomiyasu; Yasuo Kanetake
Archive | 2016
Naoaki Tsurumi; Yasuo Kanetake