Hirotaka Otake

GaN-Based Trench Gate Metal Oxide Semiconductor Field Effect Transistors with Over 100 cm2/(V s) Channel Mobility

Enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs) with trench gate structures have been developed. These MOSFETs show excellent DC characteristics with on-voltage of 5.1 V, i.e., enhancement-mode operation and extremely high channel mobilities of 133 cm2/(V s). This structure enables us to realize vertical switching devices with high breakdown voltage and highly integrated low on-resistance with the usage of excellent physical parameters of GaN. This excellent performance of these devices breaks though the realization of GaN-based power switching transistors.

Three-Phase LLC Series Resonant DC/DC Converter Using SiC MOSFETs to Realize High-Voltage and High-Frequency Operation

SiC MOSFETs are applied to constitute a three-phase, 5-kW LLC series resonant dc/dc converter with isolation transformers. A switching frequency of around 200 kHz for the transistors successfully reduces the volume of these isolation transformers, whereas insulated-gate bipolar transistors (IGBTs) are not capable of achieving such a high switching speed. The high-voltage tolerance of SiC MOSFETs, 1200 V, enables increasing the input voltage up to 600 V. High-voltage tolerance, on the other hand, is not compatible with low on-resistance for Si MOSFETs. A three-phase circuit topology is used to achieve up to 5 kW of power capacity for the converter and reduce per-phase current at the same time. Current-balancing transformers among these three phases effectively suppress a maximum peak current from arising in the circuit, a technique that miniaturizes the input and output capacitances. The conversion efficiency of the converter reaches 97.6% at 5-kW operation.

The mechanism of parasitic oscillation in a half bridge circuit including wide band-gap semiconductor devices

This paper focuses on revealing the mechanism of parasitic oscillation observed when SiC MOSFETs (metal-oxide-semiconductor field-effect transistors) operate in halfbridge configuration. The relatively large parasitic feed-back capacitance (Cgd) of SiC MOSFETs, especially if the transistors have a low threshold voltage, enhances unintentional turn-on of the device, entailing parasitic oscillation in a half bridge circuit. The wide-band gap semiconductor power device should possess a structure of as low Cgd as possible in addition to a device-specific circuit design, if the general advantage of wide band-gap power devices is utilized to facilitate high-speed switching.

Reduction in threshold voltages in GaN-based metal oxide semiconductor field effect transistors

The dc characteristics, such as on-resistances (Ron) and threshold voltages (Vth), of gallium nitride-based metal oxide semiconductor field effect transistors with vertical trench gates have been theoretically derived. The optimized acceptor density and the thickness of p-type layers for n channels (channel length) were estimated to be 3×1017cm−3 and 0.5μm, respectively, in order to realize Ron in the sub-mΩcm2 range. On the other hand, this resulted in a high Vth of 18V due to the wide bandgap. To achieve low Ron and moderate Vth less than 10V simultaneously, the insertion of an additional p−-type or n-type layer with finite thickness between the gate insulator and the p-type layer was suggested.

A study on packaging design of SiC power module using near-field magnetic scanning techniques

This report focuses the current distribution in a module identifiedwith magnetic near-field intensity for optimizing layout and packaging design of silicon carbide (SiC) power module. This measurement methodology can visualize the practical current distribution on a wiring pattern in a module and can estimate the effect of snubber capacitor in a DC-link of half-bridge to suppress the voltage overshoot and ringing oscillation.

A study on wiring pattern design for intelligent SiC power module with PEEC method

The fast switching operation of wide-bandgap power semiconductor devices deteriorates the Electromagnetic interference (EMI) noise characteristics of a power converter. The parasitic inductance in a power module is one cause of noise generator. This paper calculates parasitic inductance in a wiring pattern of module with Partial Element Equivalent Circuit (PEEC) method, and evaluates the current distribution in a module by magnetic near-field intensity measurement to discuss the suitable wiring pattern design for intelligent silicon carbide (SiC) power module.

A flyback converter using power MOSFET to achieve high frequency operation beyond 13.56 MHz

This paper discusses the development of 5-watts-class flyback converter which can operate at switching frequencies from 1 to 16 MHz. In order to analyze fast switching operations, the input and output voltages with currents are measured for estimating the converter. The self-induced soft switching operation is experimentally investigated at a ringing frequency caused by parasitic components, including junction capacitances in SiC MOSFET.

Detailed Investigation of GaN Metal-Insulator-Semiconductor Structures by Capacitance-voltage and Deep Level Transient Spectroscopy Methods

Interface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency. In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window. Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).