Masahiko Yoshimoto

A 100-MHz 2-D discrete cosine transform core processor

A 100-MHz two-dimensional discrete cosine transform (DCT) core processor applicable to the real-time processing of HDTV signals is described. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with sufficient accuracy to satisfy the specifications in CCITT recommendation H.261. The core integrates about 102 K transistors and occupies 21 mm/sup 2/ using 0.8- mu m double-metal CMOS technology. >

A 64Kb full CMOS RAM with divided word line structure

An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed.

A 50 ns video signal processor

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538 k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0- mu m double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.<<ETX>>

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment. >

Circuit device having a self-testing function and a testing method thereof

A semiconductor integrated circuit has a plurality of circuits (2 and 5) to be tested for verification of operation thereof and first, second and third scanning registers (1, 4 and 6) to be used for self-testing, and it further has a register (3) for delay. In operation, predetermined test data is inputted to each of the first and second scanning registers (1and 4) and then the first and second circuits (2 and 5) to be tested process those data simultaneously. Thus, testing time is saved. Although the time required for processing in the first circuit (2) to be tested is shorter than that in the second circuit (5) to be tested, the processed data can be obtained simutaneously by the delay function of the register (3).

A digital processor for decoding of composite TV signals using adaptive filtering

A CMOS pipelined video signal processor for use in digital NTSC/PAL color TV equipment, fabricated in a 2.0-/spl mu/m double-layer poly-Si CMOS technology, is discussed. A picture quality enhancement is achieved by using newly developed filter functions which include an intrafield adaptive separation of composite signals into the luminance, Y, and chrominance, C, spectra, and an adaptive contour compensation. Also integrated are the Y-signal-processing functions, e.g., the contrast setting, the black level correction, and the delay compensation. The device contains 88000 transistors and operates with a lower power of 450 mW at a system clock of 14.3(NTSC)/17.7(PAL) MHz, which is equal to four times the color subcarrier frequency. The chip dimensions are 8.12/spl times/6.45 mm/SUP 2/. The design goal was achieved through the development of a cost-effective system algorithm, CMOS pipelined logics, and an on-chip two-line-delay storage.

A highly-parallel DSP architecture for image recognition

The paper presents the architecture of a newly developed highly parallel DSP suited for realtime image recognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of optimized functional units for image recognition: SIMD processing core, a hierarchical bus, address generation unit, data memories, DMAC, link unit, and control unit. The DSP can process a 5/spl times/5 spatial filtering for 512/spl times/512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.5/spl times/14.5 mm/sup 2/ single-chip, using 0.5 um CMOS technology. In the paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.