Yasushi Kasa
Advanced Micro Devices
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Publication
Featured researches published by Yasushi Kasa.
symposium on vlsi circuits | 1996
Johnny Chen; Tiao-Hua Kuo; Lee Cleveland; C.K. Chung; Nancy Leong; Yong K. Kim; Takao Akaogi; Yasushi Kasa
This paper describes a 80 ns, 2.7 V to 3.6 V single voltage supply 8 Mb/spl times/16 flash memory. It uses a high speed Vcc detector to control the wordline boost level and an intelligent programming algorithm to optimize the program time. Erase is achieved by a new low Vcc negative charge pump. The device is fabricated using a 0.5 /spl mu/m design rule, double layer metal, dual layer polysilicon, and triple well CMOS. The single transistor cell size is 1.7/spl times/1.7 /spl mu/m/sup 2/. The memory cell uses a conventional drain side channel hot electron for programming and negative gate Fowler-Nordheim tunneling on the source side for erase.
Archive | 1999
Tiao-Hua Kuo; Yasushi Kasa; Johnny Chen
Archive | 2001
Tiao-Hua Kuo; Yasushi Kasa; Nancy Leong; Johnny Chen; Michael A. Van Buskirk
Archive | 2000
Yasushi Kasa; Guowei Wang
Archive | 1999
Tiao-Hua Kuo; Yasushi Kasa; Nancy Leong; Johnny Chen; Michael A. Van Buskirk
Archive | 1999
Yasushi Kasa; Johnny Chen; Guowei Wang; Tiao-Hua Kuo
Archive | 2000
Yasushi Kasa; Ming-Huei Shing
Archive | 1998
Tiao-Hua Kuo; Yasushi Kasa; Nancy Leong; Johnny Chen; Michael A. Van Buskirk
Archive | 1998
Yong K. Kim; Yasushi Kasa
Archive | 1999
Tiao-Hua Kuo; Yasushi Kasa; Nancy Leong; Johnny Chen; Michael A. Van Buskirk
