Yasushi Umezawa

A Single-Chip, 10-Gigabit Ethernet Switch LSI for Energy-Efficient Blade Servers

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. As a virtualization platform, a large-scale blade server is suitable because it can hold a dozen blades in a chassis with well managed configuration, enabling easy provisioning. To realize an energy-efficient blade server, the network component must deliver both high performance and reduced power consumption. We developed the fifth generation single-chip 10GbE switch LSI that supports 26 10GbE ports with built-in 10 Gb/s serial back plane interfaces. Using this highly integrated switch LSI, we also developed a single-wide 10GbE switch blade for the blade server. The switch blade delivers 100 percent more performance per watt than other 10GbE switch blades in the industry. This paper describes the features of the switch LSI, the high-speed IO circuit of its built-in interfaces and 10GbE switch blade.

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel

In multi-Gb/s wireline communications, equalizers are used to compensate for channel-induced signal distortion in order to stretch the maximum distance of transmission. Both amplitude and phase can be distorted in a channel. Amplitude distortion is a frequency-dependent attenuation due to skin effect and dielectric loss, causing inter-symbol-interference (ISI). A transmitter (TX) discrete-time pre-emphasis (PE) filter, a receiver (RX) continuous-time Linear Equalizer (LE), and an RX Decision-Feedback Equalizer (DFE) are generally used to cancel ISI. At 10Gb/s or higher data rate, equalizers for up to 33 to 39dB Nyquist loss and up to 20 to 25dB adapted loss range were reported [1–3]. On the other hand, how to compensate phase distortion is not clearly understood in practical circuit design. Theoretically, if a channel has minimum-phase-likecharacteristics, phase distortion is automatically co-equalized with amplitude distortion by a minimum-phase equalizer [4]. While this is the case for high-speed cables [5], it is not for PCB traces, because a non-minimum-phase equalizer, e.g., a PE with a pre-cursor tap, produces lower BER over a high-loss PCB channel than a minimum-phase equalizer, e.g., a PE without a pre-cursor tap. Thus the IEEE 10Gb Ethernet standard for backplanes adopted 3-tap PE with a precursor tap [6]. However, adaptive phase equalization in hardware has not been reported in the literature.

A Formal Verification Methodology for Checking Data Integrity

Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verification is to define good verification scopes; we should define clearly what to be verified formally upon designs under test. We considered the following three practical requirements when we defined the scope of formal verification. It should be: (a) hard to verify; (b) small to handle; and (c) easy to understand. Our novel approach is to break down generic properties for the system into stereotype properties in block level and to define requirements for Verifiable RTL. Consequently, each designer instead of verification experts can describe properties of the design easily, and formal model checking can be applied systematically and thoroughly to all the leaf modules. During the development of a component chip for server platforms, we focused on RAS (reliability availability and serviceability) features and described more than 2000 properties in PSL. As a result of the formal verification, we found several critical logic bugs in a short time with limited resources, and successfully verified all of them. This paper presents a study of the functional verification methodology.