Yoichi Koyanagi

A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Maximum baud rate of electrical signaling over backplanes is limited by reflection and crosstalk noise at connectors as well as ISI caused by frequency-dependent dielectric loss. A DFE is an effective circuit to alleviate ISI without amplifying noise. A multi-tap DFE is often used in order to cancel long-tail ISI [1–3]. However, multiple DFE taps may limit maximum operation speed due to analog feedback when using non-speculative taps [1,2], or increase power and area exponentially when using multiple speculative taps [3]. Another approach is a combination of a 1-tap speculative DFE to get faster speed and a linear equalizer (LE) to cancel the long-tail ISI [4,5]. Adaptive control is challenging when combining LE and DFE, because the relationship between LE and DFE must be taken into account [5], and the sign-sign-least-mean-square (SS-LMS) algorithm [7] that is commonly used in DFEs is not applicable to some types of LE, or at the cost of increased power and area for parallel signal paths in LE [6]. The zero-forcing (ZF) algorithm for analog filters [8] is applicable to any type of LE, but it needs an ADC and a large amount of logic to perform matrix multiplication. A heuristic algorithm [5] requires an eye measurement circuit, microcontroller, and control software.

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS

Standards such as OIF CEI-25G, CEI-28G and 32G-FC require transceivers operating at high data rates over imperfect channels. Equalizers are used to cancel the inter-symbol interference (ISI) caused by frequency-dependent channel losses such as skin effect and dielectric loss. The primary objective of an equalizer is to compensate for high-frequency loss, which often exceeds 30dB at fs/2. However, due to the skin effect in a PCB stripline, which starts at 10MHz or lower, we also need to compensate for a small amount of loss at low frequency (e.g., 500MHz). Figure 2.1.1 shows simulated responses of a backplane channel (42.6dB loss at fs/2 for 32Gb/s) with conventional high-frequency equalizers only (4-tap feed-forward equalizer (FFE), 1st-order continuous-time linear equalizer (CTLE) with a dominant pole at fs/4, and 1-tap DFE) and with additional low-frequency equalization. Conventional equalizers cannot compensate for the small amount of low-frequency loss because the slope of the low-frequency loss is too gentle (<;3dB/dec). The FFE and CTLE do not have a pole in the low frequency region and hence have only a steep slope of 20dB/dec above their zero. The DFE cancels only short-term ISI. Effects of such low-frequency loss have often been overlooked or neglected, because 1) the loss is small (2 to 3dB), 2) when plotted using the linear frequency axis which is commonly used to show frequency dependence of skin effect and dielectric loss, the low-frequency loss is degenerated at DC and hardly visible (Fig. 2.1.1a), and 3) the long ISI tail of the channel pulse response seems well cancelled at first glance by conventional equalizers only (Fig. 2.1.1b). However, the uncompensated low-frequency loss causes non-negligible long-term residual ISI, because the integral of the residual ISI magnitude keeps going up for several hundred UI. As shown by the eye diagrams in the inset of Fig. 2.1.1(b), the residual long-term ISI results in 0.42UI data-dependent Jitter (DDJ) that is difficult to reduce further by enhancing FFE/CTLE/DFE, but can be reduced to 0.21UI by adding a low-frequency equalizer (LFEQ). Savoj et al. also recently reported long-tail cancellation [2].

AP1000+: architectural support of PUT/GET interface for parallelizing compiler

The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+.

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

A 56-Gb/s receiver front-end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with a bit error rate of less than 10-12 with a 0.4UI margin in the bathtub curve. It occupies 0.27mm2 and consumes 177mW of power from a 0.9-V supply.

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

Fabricated in 90nm CMOS, the chip consumes 545mW and has a pattern-balancing adaptive equalizer that is stable for any data patterns including those with a strong peak component at a single frequency. The adaptive equalizer yields a gain at fs/2 relative to fs/16 varying from -1.7 to 2.2dB for any 8B10B encoded Ethernet frames filled with a fixed data byte

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver.

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current standards. Though transceivers for a data rate over 25Gb/s have been reported [1-3], designing clock-generating circuits for the receiver front-end is a significant challenge. In a phase interpolator (PI) commonly used in conventional receivers for a multi-channel configuration, both the linearity and frequency characteristics of the circuit affect the interpolation accuracy since it dynamically interpolates between reference clock signals supplied from a PLL, making the design more difficult. Blind-clock ADC-based receivers [4] eliminate the need for a clock-phase-adjusting circuit, but the area and power overheads are large due to high-sampling-rate ADCs. To address these issues, we fabricate and test a 28nm CMOS blind-clock receiver that performs phase tracking by using a data interpolator (DI). We confirm error-free operation of the receiver up to 32Gb/s with power consumption of 308.4mW from a 0.9V power supply.

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

The 10th generation SPARC64™ processor named SPARC64 X contains 3-billion transistors on a 588mm2 die fabricated in an enhanced 28nm high-κ metal-gate (HKMG) CMOS process, with 13 layers of copper interconnect with low-κ dielectrics. More stress control, SiGe improvement and S/D optimization achieve about 10% higher performance than the standard 28nm high performance (28HP) process. SPARC64 X runs at 3.0GHz and consists of 16 cores, shared 24MB level 2 (L2) cache, four channels of 1.6GHz DDR3 controller, two ports of PCIe Gen3 controller, and five ports of system interface controller. ccNUMA is adopted as its memory system, and a cache coherence control unit for multi-chip systems with up to 64 processors is integrated into L2 cache control circuitry for lower latency and reduced area and power consumption.

A Single-Chip, 10-Gigabit Ethernet Switch LSI for Energy-Efficient Blade Servers

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. As a virtualization platform, a large-scale blade server is suitable because it can hold a dozen blades in a chassis with well managed configuration, enabling easy provisioning. To realize an energy-efficient blade server, the network component must deliver both high performance and reduced power consumption. We developed the fifth generation single-chip 10GbE switch LSI that supports 26 10GbE ports with built-in 10 Gb/s serial back plane interfaces. Using this highly integrated switch LSI, we also developed a single-wide 10GbE switch blade for the blade server. The switch blade delivers 100 percent more performance per watt than other 10GbE switch blades in the industry. This paper describes the features of the switch LSI, the high-speed IO circuit of its built-in interfaces and 10GbE switch blade.

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI

Integrated photonic interconnect technology is free from the bandwidth-distance limitation that intrinsically exists in electrical interconnects, promising a disruptive alternative for next-generation scalable data centers. Silicon photonic platforms have been reported based on monolithic and hybrid integration. Monolithic systems mitigate integration overhead but require compromise in either electronic or photonic device performance [1,2]. Hybrid integration allows for independent process selection for each device so that overall system can potentially achieve the best performance [3]. This paper presents a hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology. A pseudo-differential driver with pre-emphasis enables an 800MHz bandwidth (BW) carrier-injection ring modulator to operate at 25Gb/s with power efficiency of 2.9pJ/b. A TIA implements two BW-enhancement techniques: a regulated-cascode (RGC) input stage with shunt-shunt feedback and T-coil inductive peaking, and a hybrid offset calibration, achieving 25Gb/s with power efficiency of 2.0pJ/b and a sensitivity of -8.0dBm OMA.