Yejia Di

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

The write performance of flash memory has been degraded significantly due to the recent density-oriented advancements of flash technology. Techniques have been proposed to improve the write performance by exploiting the varying strength of a flash block in its different worn-out stages. A block is written with a faster speed when it is new and strong, and gradually will be written with slower speeds as it is aging and becomes weak. Motivated by these works, this brief proposes a new technique by exploiting the significant process variation among flash blocks introduced by the advanced technology scaling. First, a write speed detection approach is proposed to identify the strength of each block. Then, a heuristic approach is proposed to exploit the speed variation among blocks for write performance improvement. A series of trace-driven simulations shows that the proposed approach generates substantial write performance improvement over state-of-the-art approaches by 30% on average.

Exploiting process variation for retention induced refresh minimization on flash memory

Solid state drives (SSDs) are becoming the default storage medium with the cost dropping of NAND flash memory. However, the cost dropping driven by the density improvement and technology scaling would bring in new challenges. One challenge is the overwhelmingly decreasing retention time. The duration of time for which the data written in flash memory cells can be read reliably is called retention time. To deal with the decreasing retention time, refresh has been highly recommended. However, refresh will seriously hurt the performance and lifetime, especially at the end life of flash memory. The second challenge is the process variation (PV). Significant PV has been observed in flash memory, which introduces large variations in the endurance of flash blocks. Blocks with high-endurance can provide long retention time, while the retention time is short for low-endurance blocks. Considering these two challenges, a novel refresh minimization scheme is proposed for lifetime and performance improvement. The main idea of the proposed approach is to allocate high-endurance blocks to the data with long retention time requirement in priority. In this way, the refresh operations can be minimized. Implementation and analysis show that the overhead of the proposed work is negligible. Simulation results show that both the lifetime and performance are significantly improved over the state-of-the-art scheme.

An Efficient Cache Management Scheme for Capacitor Equipped Solid State Drives

Within SSDs, random access memory (RAM) has been adopted as cache inside controller for achieving better performance. However, due to the volatility characteristic of RAM, data loss may happen when sudden power interrupts. To solve this issue, capacitor has been equipped inside emerging SSDs as interim supplier. However, the aging issue of capacitor will result in capacitance decreases over time. Once the remaining capacitance is not able to write all dirty pages in the cache back to flash memory, data loss may happen. In order to solve the above issue, an efficient cache management scheme for capacitor equipped SSDs is proposed in this work. The basic idea of the scheme is to bound the number of dirty pages in cache within the capability of the capacitor. Simulation results show that the proposed scheme achieves encourage improvement on lifetime and performance while power interruption induced data loss is avoided.

Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory

Reliability has been a challenge in the development of NAND flash memory, due to its technology size scaling and bit density improvement. To ensure the data integrity, error correction codes (ECC) with high error correction capability have been suggested. However, much higher costs will be introduced which cannot be supported for cost-limited consumer-level flash memory. Thus, low-cost ECCs are usually applied. In this work, a reliability improvement scheme is proposed for low-cost ECC enabled consumer-level flash memory. The scheme is motivated by the finding that low-cost ECC is able to protect shortened encoded data with improved reliability. This is because that the less the encoded data are, the less the errors will be occurred. With this motivation, a design is proposed to construct the shortened data case for a low-cost ECC when it cannot be able to provide the reliability requirement. Second, two relaxation approaches are proposed to relax the space reduction as it has bad effects on flash memory. A model guided evaluation is finally presented, and the results show that the lifetime can be significantly improved with little space reduction.

Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems

With the development of bit density and technology scaling, the process variation (PV) has become much severe on NAND flash memory. As PV presents reliability among flash blocks, which causes read performance variation to read data on different blocks. This paper proposes to improve read performance of LDPC based flash memory by exploiting the reliability characteristics of PV. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Then, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability and move read-cold data to blocks with low reliability. Experiment results show that, with negligible overhead, the proposed scheme is able to significantly improve the read performance.

Exploiting Chip Idleness for Minimizing Garbage Collection—Induced Chip Access Conflict on SSDs

Solid state drives (SSDs) are normally constructed with a number of parallel-accessible flash chips, where host I/O requests are processed in parallel. In addition, there are many internal activities in SSDs, such as garbage collection and wear leveling induced read, write, and erase operations, to solve the issues of inability of in-place updates and limited lifetime. When internal activities are triggered on a chip, the chip will be blocked. Our preliminary studies on several workloads show that when internal activities are frequently triggered, the host I/O performance will be significantly impacted because of the access conflict between them. In this work, in order to improve the access conflict induced performance degradation, a novel access conflict minimization scheme is proposed. The basic idea of the scheme is motivated by an interesting observation in SSDs: several chips are idle when other chips are busy with internal activities and host I/O requests. Based on this observation, we propose to schedule internal activities induced operations for minimized access conflict by exploiting the idleness of the multiple chips of SSDs. This approach is realized by two steps: First, read internal activities accessed data to the controller; second, by exploiting the idle chips during internal activities, write internal activities accessed data back to these idle chips. With this scheme, the internal activities can be processed with minimized access conflict to the host requests. Simulation results show that the proposed approach significantly reduces the access conflict, and in turn leads to a significant performance improvement of SSDs.

Improving read performance via selective V pass reduction on high density 3D NAND flash memory

3D NAND flash memory has been well developed due to its high density and decreasing cost compared with planar flash. However, one issue for 3D NAND flash, which has not been well solved, is its worse read disturb. The worse read disturb of 3D NAND flash stems from its much more word lines in a block. In this case, it receives much more read operations, leading to increased read disturb. Previous work proposed to relax the read disturb on planar flash through reducing the pass-through voltage, Vpass, on the unread word lines. However, this is not viable for 3D NAND flash with the increased number of word lines in a block. In this work, a new read disturb reduction scheme is proposed for 3D NAND flash. First, a read error model is presented, which demonstrates that selective Vpass reduction is a viable approach. Then, a read-hotness aware Vpass reduction scheme is proposed to improve performance without violating the reliability requirement. Simulation shows that the proposed scheme achieves encouraging performance improvement.

Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories

Appealed by the market, flash memory density is being increasingly improved, and the technology scale is being reduced. Currently, scaled multi-level-cell (MLC) flash memory has been the dominant in the global flash memory markets. However, the reliability of MLC flash memory becomes the urgent challenge, where cell-to-cell interference has been well recognized as the major error source. In this work, we propose to minimize cell-to-cell interference through exploiting the differential impacts on the multiple-bit of MLC flash memories. MLC flash memory generally has two or more bits per cell, such as 2-bit/cell or 4- bit/cell, which can be differentially interfered by neighboring cell programming. Based on the understanding of the programming characteristics of MLC flash memory, we found that higher-order bits can be higher interfered and be more significant interference sources. In order to understand the characteristics of cell-tocell interference on the multiple bits, we first present cell-to-cell interference models for multiple bits, respectively. Then based on the model, a state mapping scheme is designed to minimize cell-to-cell interference through mapping the states of high-order bits. The mapping scheme is motivated by the recent studies on the cell-to-cell interference characteristics of the multiple cell states of flash memory, where different states have varying interferences. In this case, high-order bits should be mapped from high interference states to a low one. A series of experiments show that the proposed scheme is efficient on reducing cell-to-cell interference with negligible overhead.