Yexin Deng

RRAM Crossbar Array With Cell Selection Device: A Device and Circuit Interaction Study

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I-V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation.

A physical based analytic model of RRAM operation for circuit simulation

A physical based analytic model of metal oxide based RRAM cell under DC and pulse operation modes is presented. In this model, the transport behaviors of oxygen vacancies and oxygen ions, metal conductivity, electron hopping and heat conduction and the parasitic capacitance and resistance effects are covered. The developed analytic model is verified and calibrated by measured data. Furthermore, we implement the analytic model in a 2×2 RRAM array simulation and investigate the reliability of RRAM array for the first time.

Design and optimization methodology for 3D RRAM arrays

3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

Multi-level resistive switching characteristics correlated with microscopic filament geometry in TMO-RRAM

For the first time, we report that the resistive switching behaviors of the multi-level resistance states can be influenced by the operation mode. Simulations reveal that this is due to the different geometry of the conductive filament in the multi-level resistance states stemmed from the different operation mode. Based on this understanding, improved stability and uniformity of the medium resistance states during switching process are predicted and experimentally verified.

Design guidelines for 3D RRAM cross-point architecture

Design guidelines were proposed to evaluate and optimize the 3D RRAM cross-point architecture by a full-size 3D circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3D cross-point architecture including the horizontally stacked or the vertically stacked structure were compared in terms of these metrics, revealing the advantages of the vertical RRAM structure. Then the scaling trend of the vertical RRAM based 3D array with respect to the scaling of lateral feature size, vertical electrode thickness and vertical isolation layer thickness were evaluated. The design parameters that affect the scaling trend include the metal interconnect resistance, RRAM on-state cell resistance (or the nonlinearity of the I-V). The design trade-offs are discussed considering those parameters constraints.

3D RRAM: Design and optimization

A novel vertical RRAM for 3D cross-point architecture is proposed. The design and optimization issues of the proposed vertical RRAM for 3D cross-point architecture array are addressed from both device and array levels. A double layer stacked HfOx based vertical RRAM devices with interface engineering fabricated using a cost-effective fabrication process. The excellent performances such as low reset current, fast switching speed, high switching endurance and disturbance immunity, good retention and self-selectivity are demonstrated in the fabricated HfOx based vertical RRAM devices. The opimized design guidances for the 3D cross-point architecture array are presented.

Scaling behavior of PCM cells in off-state conduction

A novel phase change memory (PCM) cell with Additional Top Electrode (ATE) is introduced to investigate the scaling behavior of the off-state with the dimension of amorphous state region. The electrical conduction in ultra-thin amorphous state layer is investigated. The trap spacing is one of the key parameters that govern the conduction mechanism and threshold voltage in the sub-threshold region which can be extracted by measuring the change in the activation energy of conduction with respect to the applied voltage. The linear dependence of the trap spacing on the dimension of amorphous state region is demonstrated, which could provide guidelines for designing ultra-thin film based PCM device.

Optimization of Conductive Filament of Oxide-Based Resistive-Switching Random Access Memory for Low Operation Current by Stochastic Simulation

Large switching current is a great challenge for scaling down of the oxide-based resistive random access memory devices to realize high density and low power memory array. In this paper, large operation current caused by the current overshoot effect during forming process is investigated using a stochastic simulator based on the percolation theory. The electrical characteristic of forming process is simulated and compared with the experimental data. Our simulation demonstrates that the current overshoot effect results in a stronger conductive filament during forming process, which will cause a larger operation current in subsequent switching cycle. Furthermore, our simulation results reveal that low sweeping rate, high ambient temperature, high doping concentration and high pre-exist oxygen vacancies (VO) concentration are beneficial to the control of conductive filament evolution and the suppression of the current overshoot effect, which is critical for low reset current and low operation power resistive-switching random access memory (RRAM).

Metal Oxide RRAM For Next Generation Mass Storage: 3D Vertical Architecture and Electrode/Oxide Interface Engineering

1 Department of Electrical Engineering and Center for Integrated Systems, Stanford University, Stanford, CA 94305, USA 2 Institute of Microelectronics, Peking University, Beijing 100871, China 3 Institute of Microelectronics, Tsinghua University, Beijing 100084, China 4 Tsinghua National Laboratory for Information Science and Technology (TNList), Tsinghua University, Beijing 100084, China E-mail: *hongyuc@stanford.edu, hspwong@stanfrod.edu

Size analysis of multilevel RRAM array and optimization of device and circuit characteristics

Multilevel RRAM array is one of the most promising candidates of next generation high density memory technology. In this paper, we investigate the size limitation of multilevel 1D1R RRAM array based on circuit simulation. Optimization of device characteristics and operation mode is obtained to increase the array size and the circuit performance. This work may be helpful for multilevel array design and application.