Yi-Wen Wang

Robust fixed-outline floorplanning through evolutionary search

In this paper, we address the pratical problem of fixed-outline VLSI floorplanning with minimizing the objective of area. This problem was shown significantly much more difficult than the well-researched floorplan problems without fixed-outline regime [1]. We successfully develop an algorithm with evolutionary search to efficiently handle the fixed-die floorplanning problem and achieve near 100% successful probability, on the average.

An efficient genetic algorithm for slicing floorplan area optimization

In this paper, we develop a new genetic algorithm that can efficiently solve the floorplan area optimization problem. The algorithm merges the properties of encoding schemes of slicing trees and the evolutional mechanism of genetic algorithms. A novel genetic operator, which always inherits good properties from ancestors in the algorithm, is proposed to effectively explore solution space. Experimental results show that the developed algorithm achieves comparable computation time and performance quality to the nonslicing state-of-the-art ones.

GPE: a new representation for VLSI floorplan problem

In this paper, we propose a new representation of VLSI floorplan and building block problem. The representation is the generalization of Polish expression. By proposing a new relational operator, the representation can efficiently reuse some area that cannot be utilized if only having vertical and horizontal operators defined in Polish expression, and is able to present non-slicing structural floorplan. The experimental results show that the representation achieves promising area utilization in commonly used MCNC benchmark circuits.

Fixed-outline floorplanning using robust evolutionary search

Typical floorplanning concerns a series of objectives, such as area, wirelength, and routability, etc., with various aspect ratios of modules in a free-outline regime. However, in a hierarchical design flow for very large ASICs and SoCs, a floorplan can be completely useless for a situation where its outline is dissatisfied. In this paper, we study the fixed-outline floorplanning problem that is more applicable to the hierarchical design style. We develop an efficient algorithm based on robust evolutionary search and achieve substantially improved success rate. We also propose a new approach to handle soft modules to further adjust the generated floorplan to fit into the prescribed chip outline. The effectiveness of our methods is demonstrated on several large cases of MCNC and GSRC benchmarks.

Modem floorplanning with abutment and fixed-outline constraints

The typical floorplanning problem concerns a series of objectives, such as area, wirelength and routability, etc., without any specific constraint in a free-outline style. Entering the SOC era, however, modern floorplanning takes more care of providing extra options to place dedicated modules in the hierarchical designs, such as abutment, boundary and fixed-outline constraints, etc. It has been empirically shown that any of the modern constraints extremely restricts the solution space, that is, a large number of randomly generated floorplans might violate the constraint. This paper addresses modern floorplanning with abutment and fixed-outline constraints. In order to search the drastically limited solution space, we first investigate the feasible properties of a slicing floorplan with abutment constraint. The properties, coupled with an efficient evolutionary search algorithm provide the way to produce floorplans with abutment constraint. We then extend the algorithm with minor modification to enable the abutment floorplans to be gradually fitted into the desirable fixed outline. The methods are verified by using the MCNC and GSRC benchmarks, and the empirical results show that our methods can obtain promising solutions in a short time.

VLSI floorplanning with boundary constraints using generalized polish expression

Abstract Module floorplanning/placement considering boundary constraints is practical and crucial in modern designs because designers may want to place some I/O involved modules along the chip boundary to minimize both chip area and off‐chip connections. In this paper, a boundary information checking algorithm based on a general structure representation, called Generalized Polish Expression (GPE), is proposed. The algorithm, coupled with efficient perturbations in GPE, effectively produces solutions that satisfy both the boundary constraints and small chip area requirement. The experimental results have shown good performance from our approach on several commonly used MCNC benchmarks.

Fast multilevel floorplanning for large scale modules

With the advance of deep sub-micron, current methods are not effective to obtain acceptable layout for large scale modules. Hence, it is important to provide designers of SoC with a powerful floorplanner. In traditional approaches, it is common to simultaneously utilize clustering and declustering technologies, i.e. multiple phases to refine the solution quality. We propose a top-down multilevel genetic floorplanning algorithm to handle the floorplanning and packing for large scale modules. The algorithm is simple and only needs the clustering phase. Experimental results show significantly better running time and promising solutions in comparison with other state-of-the-art research works.

Memory Models for an Application-Specific Instruction-set Processor Design Flow

To optimize system performance for a specific target application, embedded system designers may add some new instructions, called application-specific instructions (ASIs), by automatic design flow. In past days, most application-specific instruction-set processor (ASIP) researches focus on reducing instruction latency to improve performance regardless of the impact of memory access. In this paper, a design flow is proposed to automatically generate ASIs and to compare the performance between considering register transferring and regardless of it. The experiment results show the proposed approach can achieve up to 14% performance improvement and 10% memory access reduction comparing to no register transferring consideration.

Application-Specific Instruction Generation for SOC Processors

Application-specific instruction set processors assures good tradeoff between efficiency and flexibility in SOC design. However, it is difficult to obtain the extended instructions by manual designs for large programs with various design constraints. A two-phase design flow is proposed to automatically generate application specific instructions to achieve the better performance. Firstly, we translate various applications from C programs to a control/data flow graph. Secondly, a set of proposed algorithms is utilized to analyze the dependency of instructions in the data flow graph as well as to generate and evaluate application-specific instructions. Experimental results indicate that the MiBench applications can be improved about 1.5 to 3.18 times speedup using our generated application-specific instructions.

MODERN FLOORPLANNING WITH BOUNDARY AND FIXED-OUTLINE CONSTRAINTS VIA GENETIC CLUSTERING ALGORITHM

Typical floorplanning problem concerns a series of objectives, such as area, wirelength and routability, etc., without any specific constraint in a free-outline style. Entering SOC era; however, modern floorplanning takes more care of providing extra options, such as boundary constraint for I/O connections and fixed-outline constraint for hierarchical designs. It has been empirically shown that one of the modern constraints extremely restricts the solution space; that is, a large number of randomly generated floorplans might be infeasible. This paper tackles modern floorplanning with both boundary and fixed-outline constraints. A novel genetic clustering algorithm was proposed to guarantee to produce slicing floorplans with satisfying boundary constraint. By analyzing the properties of the slicing floorplan, the algorithm is effective to cluster the boundary-constrained modules into four constrained sub-floorplans. Afterward, the four sub-floorplans were combined to satisfy the boundary constraint. We then extend the algorithm with minor modification to enable the slicing floorplans with boundary constraint to be gradually fit into the desirable fixed outline. The methods were verified by using the MCNC and GSRC benchmarks, and the empirical results show that our methods can obtain promising solutions using short time.