Ching-Hwa Cheng

A panoramic endoscope design and implementation for Minimally Invasive Surgery

Minimally Invasive Surgery (MIS) is a current major technique for surgery. Compared to traditional methods of surgery, MIS can reduce the post-surgical recovery time, cost and pain to patients due to surgery. It is therefore in the interest of doctors and patients. There are several MIS techniques that have been widely accepted for diagnosis and treatment in most hospitals, such as hysteroscopy, laparoscopy, and colon endoscopy. The major problem of MIS is a narrow field of vision. We develop and validate a MIS Panoramic Endoscope (MISPE) to provide doctors with broad fields of view. MISPE features a combination of image overlapping and image stitching. The panoramic image apparatus has two side-by-side endoscopic lenses that provide wide-angle inputs for image stitching. MISPE can provide doctors with panoramic images, so that doctors can easily discriminate the organs positions between surgery operations. Experimental results show that MISPE can enhance the image size up to 155%. The whole system is validated by personal computer. The animal vivo experimental videos have been successfully validated.

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video

This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2∼328mW in decoding CIF∼HD1080 videos at 3.75∼30fps when operating at 1∼150MHz, respectively.

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications

This article proposes a low-cost, low-power multistandard video decoder for high definition (HD) video applications. The proposed design supports multiple-standard (JPEG baseline, MPEG-1/2/4 Simple Profile (SP), and H.264 Baseline Profile (BP)) video decoding through interactive parsing control and common parameter bus interface. In order to reduce hardware cost, the shared adder-based structure and reusable data management are proposed to achieve hardware sharing and reduce internal memory size, respectively. In addition, the proposed design is optimized through reducing memory bandwidth by increasing both data reuse amount and burst length of memory access as well as eliminating cycle overhead in data access for supporting HD video decoding with single AHB-based SDR memory. The proposed 252Kgates/4.9kB/71mW/0.13μm multi-standard video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120MHz for real-time HD1080 video decoding with single AHB-based SDR memory.

A low-power vdd-management technique for high-speed domino circuits

A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.

A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video

The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.

A full-synthesizable high-precision built-in delay time measurement circuit

Delay testing has become a major issue for manufacturing advanced Systems on a Chip. Automatic Test Equipment and scan techniques are usually applied in delay testing. However, the circuits under test have many circuit paths and dependent input patterns; it is hard to measure delay times accurately, especially when debugging small delay defects. We propose a Built-In Delay Measurement (BIDM) circuit that is modified from Vernier Delay Lines. All digitally designed BIDMs with small area overhead can be easily embedded within testing circuits. BIDMs can be used to record the data propagation delay times within circuit path segments, for delay testing, diagnosis, and calibration requirements internal to the chip. Our BIDM was implemented in a 32bit error correction circuit by a chip using TSMC 0.18u technology. The instruments measured results showing that the BIDM chip correctly reported the CUT segment path delay times. The chip measurement results were a 95.83% match to the postlayout SPICE simulation values. This BIDM makes it possible to debug small delay defects in chips.

Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism

The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism is successfully validated using TSMC 0.18 technology. The test chip shows ×2.7 performance improvement compared to the conventional static CMOS logic design.

A variable-voltage low-power technique for digital circuit system

A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising and falling signals fanin FDCA to generate an adjustable high-low signal to control VFA generates high-low cycling swing voltage. When the clock is at positive-level, a generic positive-edge digital circuit will need large operation current. CK-Vdd supply high-voltage to the digital circuit at this time. On the other hand, when the clock signal transfers to the low-level, CK-Vdd can supply low-voltage to reduce power consumption. From reducing the supply current to the digital circuit at low-level clock, the digital circuit power consumption can be reduced. We implement the CK-Vdd technique in a H.264 video decoder test chip based on TSMC 90 nm CMOS process. The result shows that when CK-Vdd voltage is 0.7v ~ 0.9v it can save average 32% power consumption. To the maximum, decoder chip can save as high as 45% power consumption.

A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications

Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage (HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage.

A wireless panoramic endoscope system design and implementation for minimally invasive surgery

Minimally Invasive Surgery (MIS) is a current major surgery technique. A chief problem with MIS is its narrow field of vision. A wireless MIS Panoramic Endoscope (WMISPE) is developed and implemented to provide doctors with broad fields of view. A WMISPE features a combination of video overlapping and video stitching. The panoramic video apparatus has two side-by-side endoscopic lenses that provide wide-angle inputs for video stitching. A WMISPE can provide doctors with panoramic videos, so that they can easily discriminate an organs position between surgical operations. Experimental results show that WMISPE can enhance the video size to 158%. A low-power multi-mode video decoder (MMVD) is used to validate the stitching videos. The whole system is validated by personal computer, an embedded system, and an H.264 decoder chip. The test chip is successfully validated after system integration, and obtains about a 24% reduction in power consumption, which is better than that of the same design using a single supply voltage. The animal vivo experimental videos have been successfully validated.