Yihan Chen

Synthesis and interface characterization of CNTs on graphene

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C-C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C-C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

3-D Resistance Model for Phase-Change Memory Cell

In this paper, a 3-D resistance model is proposed for phase-change (PC) memory cell based on cell geometry and RESET current. Explicit expression is developed for PC radius in terms of RESET current, cell geometry, and material property. Conformal mappings are used for SET and RESET resistance calculation in 2-D models, which solve the problem of current crowding in structures with complex boundary condition. In the 3-D model development, additional spreading resistance is considered, together with the bulk resistance stemmed from 2-D model to form the eventual complete expression. Models show good consistency with finite element simulation and experimental data.

Interface engineering to enhance phase change memory programmability

Despite the promise for resistive phase-change memory to be used in the BEOL memory integration, achieving low current programming and rapid thermal cycle management are still the main barriers in term of operation. In this work, different methods to reduce the programming current are examined with respect to their effects on thermal cycling during SET and RESET. In particular, the discussion will focus on the engineering of the electrode to phase-change material interface to achieve low programming current. Experimental demonstration and thermal simulation data are used to illustrate the concept and explain the device behaviors.

Ohmic contact formation between Ge 2 Sb 2 Te 5 phase change material and vertically aligned carbon nanotubes

The contact property between Ge2Sb2Te5 (GST) with vertical carbon nanotubes (CNTs) is studied in this work. By careful catalyst design and process optimization, we have demonstrated the formation of ohmic contact between the CNT and the GST material. The developed process is CMOS compatible and can be used for form phase change memory over the vias in the interconnect layers.

Low Power Phase Change Memory With Vertical Carbon Nanotube Electrode

Phase change memory (PCM) formed by Ge2Sb2Te5 (GST) on vertical carbon nanotube (CNT) filled contact plug is demonstrated in this paper. In order to achieve compatibility with the underlying process, the CNTs are synthesized using nickel catalyst at a low temperature. Reasonable contact characteristics between the CNTs and GST are achieved without material compatibility problem. Due to the small contact size of the CNT to the phase change material, a significant reduction in programming power is achieved compared to metal contact at the same via size. The temperature simulation result shows that the CNT filled via helps to reduce the programing area. The fabricated PCM on CNT filled via is able to endure more than 104 SET/RESET cycles without observable degradation.

Modeling current reduction/or PCM cell with thermal buffer layer

In this work, a model is developed for RESET current reduction calculation for phase-change memory (PCM) cell with thermal buffer layer. Numerical simulation indicates more significant contribution of the buffer layer on heat generation than on thermal loss, supporting following model development which treats the total cell resistance as the crucial factor. The model is verified by comparison with both finite-element simulation and experimental data, hence is capable to give guidance in future buffer layer design, particularly in estimation for the limit value of current reduction and buffer layer thickness.

Atomistic simulation of phase change memory during switching

A methodology to study phase-change memory programming at atomistic level during SET and RESET operations is presented. Based on the melt-quench scheme, the molecular dynamic for amorphization and crystallization of GeTe been investigated. The time evolution of the crystal structure under different annealing and quenching conditions has been demonstrated. The final structure under different SET and RESET conditions can be predicted using the proposed method.