Mansun Chan

Highly Aligned Graphene/Polymer Nanocomposites with Excellent Dielectric Properties for High-Performance Electromagnetic Interference Shielding

Nanocomposites that contain reinforcements with preferred orientation have attracted significant attention because of their promising applications in a wide range of multifunctional fields. Many efforts have recently been focused on developing facile methods for preparing aligned graphene sheets in solvents and polymers because of their fascinating properties including liquid crystallinity and highly anisotropic characteristics. Self-aligned in situ reduced graphene oxide (rGO)/polymer nanocomposites are prepared using an all aqueous casting method. A remarkably low percolation threshold of 0.12 vol% is achieved in the rGO/epoxy system owing to the uniformly dispersed, monolayer graphene sheets with extremely high aspect ratios (>30000). The self-alignment into a layered structure at above a critical filler content induces a unique anisotropy in electrical and mechanical properties due to the preferential formation of conductive and reinforcing networks along the alignment direction. Accompanied by the anisotropic electrical conductivities are exceptionally high dielectric constants of over 14000 with 3 wt% of rGO at 1 kHz due to the charge accumulation at the highly-aligned conductive filler/insulating polymer interface according to the Maxwell-Wagner-Sillars polarization principle. The highly dielectric rGO/epoxy nanocomposites with the engineered structure and properties present high performance electromagnetic interference shielding with a remarkable shilding efficiency of 38 dB.

A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I/sub ds/, conductances and their derivatives throughout all V/sub gs/, V/sub ds/, and T/sub bs/, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on.

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm2. The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV VDO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity.

Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-mum MOS technology. It is proven experimentally that the LDO provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition. The preset output voltage, minimum unregulated input voltage, maximum output current at a dropout voltage of 200 mV, ground current and active chip area are 1 V, 1.2 V, 50 mA, 95 muA, and 140 mum times 320 mum, respectively. The full-load transient response in the no output capacitor case is faster than a micro second and is about 300 ns.

Modeling of Mutual Coupling Between Planar Inductors in Wireless Power Applications

This paper presents a compact model of mutual inductance between two planar inductors, which is essential to design and optimize a wireless power transmission system. The tracks of the planar inductors are modeled as constant current carrying filaments, and the mutual inductance between individual filaments is determined by Neumanns integral. The proposed model is derived by solving Neumanns integral using a series expansion technique. This model can predict the mutual inductance at various axial and lateral displacements. Mutual coupling between planar inductors is computed by a 3-D electromagnetic (EM) solver, and the proposed model shows good agreement with these numerical results. Different types of planar inductors were fabricated on a printed circuit board (PCB) or silicon wafer. Using these inductors, wireless power links were constructed for applications like implantable biomedical devices and contactless battery charging systems. Mutual inductance was measured for each of the cases, and the comparison shows that the proposed model can predict mutual coupling suitably.

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied

A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

A new non-quasi-static (NQS) MOSFET model, which is applicable for both large-signal transient and small-signal ac analysis, has been developed. It employs a physical relaxation time approach to take care of the finite channel charging time to reach equilibrium and the effect of instantaneous channel charge re-distribution. The NQS model is formulated independently from the dc I-V and the charge-capacitor model, thus can be easily applied to any existing simulators. The model has been implemented in the newly released BSIM3 version 3, and comparison has been made among this model, common quasi-static (QS) SPICE models and PISCES two-dimensional (2-D) numerical device simulator. While predicting accurate NQS behavior, the time penalty for using the new model is only about 20-30% more than the common QS models. It is much less than the time required by other NQS models reported. Limitations and compromises between simplicity, efficiency and accuracy are also discussed.