Wang Ling Goh

Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.

A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning

A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13-mum CMOS process, the proposed voltage-controlled ring oscillator exhibits a low phase noise of -103.4 dBc/Hz at 1 MHz offset from the center frequency of 7.64 GHz, while consuming a current of 40 mA excluding the buffer.

A 100-Channel 1-mW Implantable Neural Recording IC

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops

A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.

Low-power high-speed multiplier for error-tolerant application

In this paper, a new design concept that engaged accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, the bottleneck of conventional digital IC design techniques can be breakthrough to improve on the performances of power consumption and speed. The aim is to fulfill the need for high performance basic sequential elements with low-power dissipation which is steadily growing.

130-GHz On-Chip Meander Slot Antennas With Stacked Dielectric Resonators in Standard CMOS Technology

This work discusses the design methodologies of 130-GHz high gain and high efficiency on-chip meander slot antennas in a standard CMOS technology. In the proposed structure, stacked dielectric resonators (DRs) are placed on the top of the on-chip feeding element to form series-fed antenna array for antenna gain and efficiency improvement. The integrated antenna with double stacked DRs achieved a measured gain of 4.7 dBi at 130 GHz with a bandwidth of 11%. The antenna size is 0.8 ×0.9 mm2 and the simulation results indicate a radiation efficiency of 43%. To the best of our knowledge, this is the first demonstration of an on-chip antenna gain and efficiency enhancement through stacked DRs.

A 5-Gb/s Automatic Gain Control Amplifier With Temperature Compensation

This paper presents an automatic gain control (AGC) amplifier with temperature compensation for high-speed applications. The proposed AGC consists of a folded Gilbert variable gain amplifier (VGA), a dc offset canceller, inductorless post amplifiers, a linear open-loop peak detector (PD), an integrator, a symmetrical exponential voltage generator, and a compensation block for temperature stability. The novel temperature compensation scheme ensures the AGC stability and accuracy over -20°C-200°C by predicting the integrator biasing voltage based on the crucial blocks duplication technique. The proposed linear open loop PD combined with the linear-in-dB VGA manages the dB-linear error of less than 0.3 dB for the received signal strength indication (RSSI). The AGC chip is fabricated using a 0.13-μm SiGe BiCMOS technology. Consuming a power of 72 mW from a 1.2-V supply voltage, the fabricated circuit exhibits a voltage gain of 40 dB and a 3-dB bandwidth of 7.5 GHz. With a 215 - 1 pseudo-random bit sequence at 5-Gb/s, the measured peak-to-peak jitter is less than 40pspp across the -20°C-200°C temperature range. The low linear-in-dB error and the wide operating temperature range achieving the high-speed data input signal indicate the suitability of the proposed techniques for high-speed AGC amplifiers.

Enhanced low-power high-speed adder for error-tolerant application

The tradeoff between power consumption and speed performance has become a major design consideration when devices approach the sub-100 nm regime. It is especially critical when dealing with large data set, whereby the system is degraded in terms of power and speed. If the application can accept some errors, i.e. the application is Error — tolerant (ET), a large reduction in power and an increased in speed can be simultaneously achieved. In this paper, we shall present a novel low-power and high-speed Error-Tolerant Adder Type IV design called ETAIV. The proposed ETAIV is an enhancement of our earlier design, ETAII [1] in terms of speed and accuracy.

A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration

The performance of static CMOS circuits is superior in terms of power consumption and glitch reduction to dynamic circuits when the fan-in is small. We propose a new static dual edge-triggered flip-flop that incorporates no precharging and conditional discharging to reduce the switching activity at the internal node efficiently. Hence, the power dissipation is very much reduced. Based on simulation results derived from 0.18-/spl mu/m CMOS technology, our proposed flip-flop consumes the least power regardless of the input data activity.

A D-Band Cascode Amplifier With 24.3 dB Gain and 7.7 dBm Output Power in 0.13

This letter describes a D-band 3-stage cascode amplifier developed using the IHP 0.13 μm SiGe BiCMOS technology. The amplifier is implemented with low-loss transformer for inter-stage matching and single-to-differential transformation. The large-signal characteristics of the cascode HBT configuration are used to optimize the bias condition for highest output power and gain performance. A measured amplifier achieves a peak power gain of 24.3 dB, with a 3 dB bandwidth of 20 GHz centered at 130 GHz. The amplifier exhibits a saturated output power of 7.7 dBm and an output 1 dB gain compression point of 6 dBm with a power consumption of 84 mW. The measured noise figure is 6.8 dB at 130 GHz and stays under 8 dB over the 3 dB bandwidth. To the best of our knowledge, the proposed amplifier exhibits the highest gain and output power among the silicon-based D-band amplifiers reported so far.