Yike Hu

Nanoscale Tunable Reduction of Graphene Oxide for Graphene Electronics

Writing Conductive Lines with Hot Tips The interface within devices between conductors, semiconductors, and insulators is usually created by stacking patterned layers of different materials. For flexible electronics, it can be advantageous to avoid this architectural constraint. Graphene oxide, formed by chemical exfoliation of graphite, can be reduced to a more conductive form using chemical reductants. Wei et al. (p. 1373) now show that layers of graphene oxide can also be reduced using a hot atomic force microscope tip to create materials comparable to those of organic conductors. This process can create patterned regions (down to 12 nanometers in width) that differ in conductivity by up to four orders of magnitude. Conducting regions can be drawn on graphene oxide sheets with a heated atomic force microscope tip. The reduced form of graphene oxide (GO) is an attractive alternative to graphene for producing large-scale flexible conductors and for creating devices that require an electronic gap. We report on a means to tune the topographical and electrical properties of reduced GO (rGO) with nanoscopic resolution by local thermal reduction of GO with a heated atomic force microscope tip. The rGO regions are up to four orders of magnitude more conductive than pristine GO. No sign of tip wear or sample tearing was observed. Variably conductive nanoribbons with dimensions down to 12 nanometers could be produced in oxidized epitaxial graphene films in a single step that is clean, rapid, and reliable.

Room-temperature metastability of multilayer graphene oxide films.

Graphene oxide potentially has multiple applications. The chemistry of graphene oxide and its response to external stimuli such as temperature and light are not well understood and only approximately controlled. This understanding is crucial to enable future applications of this material. Here, a combined experimental and density functional theory study shows that multilayer graphene oxide produced by oxidizing epitaxial graphene through the Hummers method is a metastable material whose structure and chemistry evolve at room temperature with a characteristic relaxation time of about one month. At the quasi-equilibrium, graphene oxide reaches a nearly stable reduced O/C ratio, and exhibits a structure deprived of epoxide groups and enriched in hydroxyl groups. Our calculations show that the structural and chemical changes are driven by the availability of hydrogen in the oxidized graphitic sheets, which favours the reduction of epoxide groups and the formation of water molecules.

Scalable templated growth of graphene nanoribbons on SiC

In spite of its excellent electronic properties, the use of graphene in field-effect transistors is not practical at room temperature without modification of its intrinsically semimetallic nature to introduce a bandgap. Quantum confinement effects can create a bandgap in graphene nanoribbons, but existing nanoribbon fabrication methods are slow and often produce disordered edges that compromise electronic properties. Here, we demonstrate the self-organized growth of graphene nanoribbons on a templated silicon carbide substrate prepared using scalable photolithography and microelectronics processing. Direct nanoribbon growth avoids the need for damaging post-processing. Raman spectroscopy, high-resolution transmission electron microscopy and electrostatic force microscopy confirm that nanoribbons as narrow as 40 nm can be grown at specified positions on the substrate. Our prototype graphene devices exhibit quantum confinement at low temperatures (4 K), and an on-off ratio of 10 and carrier mobilities up to 2,700 cm(2) V(-1) s(-1) at room temperature. We demonstrate the scalability of this approach by fabricating 10,000 top-gated graphene transistors on a 0.24-cm(2) SiC chip, which is the largest density of graphene devices reported to date.M. Sprinkle, M. Ruan, X. Wu, Y. Hu, M. Rubio-Roy, J. Hankinson, N.K. Madiomanana, C. Berger, 2 and W.A. de Heer Georgia Institute of Technology, Atlanta, Georgia 30332-0430, USA CNRS/Institut Néel, BP166, 38042 Grenoble, France Abstract Realization of post-CMOS graphene electronics requires production of semiconducting graphene, which has been a labor-intensive process.1–5 We present tailoring of silicon carbide crystals via conventional photolithography and microelectronics processing to enable templated graphene growth on 4H-SiC{11̄0n} (n ≈ 8) crystal facets rather than the customary {0001} planes. This allows self-organized growth of graphene nanoribbons with dimensions defined by those of the facet. Preferential growth is confirmed by Raman spectroscopy and high-resolution transmission electron microscopy (HRTEM) measurements, and electrical characterization of prototypic graphene devices is presented. Fabrication of > 10,000 top-gated graphene transistors on a 0.24 cm2 SiC chip demonstrates scalability of this process and represents the highest density of graphene devices reported to date.

Large area and structured epitaxial graphene produced by confinement controlled sublimation of silicon carbide

After the pioneering investigations into graphene-based electronics at Georgia Tech, great strides have been made developing epitaxial graphene on silicon carbide (EG) as a new electronic material. EG has not only demonstrated its potential for large scale applications, it also has become an important material for fundamental two-dimensional electron gas physics. It was long known that graphene mono and multilayers grow on SiC crystals at high temperatures in ultrahigh vacuum. At these temperatures, silicon sublimes from the surface and the carbon rich surface layer transforms to graphene. However the quality of the graphene produced in ultrahigh vacuum is poor due to the high sublimation rates at relatively low temperatures. The Georgia Tech team developed growth methods involving encapsulating the SiC crystals in graphite enclosures, thereby sequestering the evaporated silicon and bringing growth process closer to equilibrium. In this confinement controlled sublimation (CCS) process, very high-quality graphene is grown on both polar faces of the SiC crystals. Since 2003, over 50 publications used CCS grown graphene, where it is known as the “furnace grown” graphene. Graphene multilayers grown on the carbon-terminated face of SiC, using the CCS method, were shown to consist of decoupled high mobility graphene layers. The CCS method is now applied on structured silicon carbide surfaces to produce high mobility nano-patterned graphene structures thereby demonstrating that EG is a viable contender for next-generation electronics. Here we present for the first time the CCS method that outperforms other epitaxial graphene production methods.

Record maximum oscillation frequency in C-face epitaxial graphene transistors.

The maximum oscillation frequency (fmax) quantifies the practical upper bound for useful circuit operation. We report here an fmax of 70 GHz in transistors using epitaxial graphene grown on the C-face of SiC. This is a significant improvement over Si-face epitaxial graphene used in the prior high-frequency transistor studies, exemplifying the superior electronics potential of C-face epitaxial graphene. Careful transistor design using a high κ dielectric T-gate and self-aligned contacts further contributed to the record-breaking fmax.

Half integer quantum Hall effect in high mobility single layer epitaxial graphene

The quantum Hall effect, with a Berry’s phase of π is demonstrated here on a single graphene layer grown on the C-face of 4H silicon carbide. The mobility is ∼20 000 cm2/V⋅s at 4 K and 15 000 cm2/V⋅s at 300 K despite contamination and substrate steps. This is comparable to the best exfoliated graphene flakes on SiO2 and an order of magnitude larger than Si-face epitaxial graphene monolayers. These and other properties indicate that C-face epitaxial graphene is a viable platform for graphene-based electronics.

Epitaxial Graphene Electronic Structure And Transport

Since its inception in 2001, the science and technology of epitaxial graphene on hexagonal silicon carbide has matured into a major international effort and is poised to become the first carbon electronics platform. A historical perspective is presented and the unique electronic properties of single and multilayered epitaxial graphenes on electronics grade silicon carbide are reviewed. Early results on transport and the field effect in Si-face grown graphene monolayers provided proof-of-principle demonstrations. Besides monolayer epitaxial graphene, attention is given to C-face grown multilayer graphene, which consists of electronically decoupled graphene sheets. Production, structure, and electronic structure are reviewed. The electronic properties, interrogated using a wide variety of surface, electrical and optical probes, are discussed. An overview is given of recent developments of several device prototypes including resistance standards based on epitaxial graphene quantum Hall devices and new ultrahigh frequency analog epitaxial graphene amplifiers.

High-resolution tunnelling spectroscopy of a graphene quartet

Electrons in a single sheet of graphene behave quite differently from those in traditional two-dimensional electron systems. Like massless relativistic particles, they have linear dispersion and chiral eigenstates. Furthermore, two sets of electrons centred at different points in reciprocal space (‘valleys’) have this dispersion, giving rise to valley degeneracy. The symmetry between valleys, together with spin symmetry, leads to a fourfold quartet degeneracy of the Landau levels, observed as peaks in the density of states produced by an applied magnetic field. Recent electron transport measurements have observed the lifting of the fourfold degeneracy in very large applied magnetic fields, separating the quartet into integer and, more recently, fractional levels. The exact nature of the broken-symmetry states that form within the Landau levels and lift these degeneracies is unclear at present and is a topic of intense theoretical debate. Here we study the detailed features of the four quantum states that make up a degenerate graphene Landau level. We use high-resolution scanning tunnelling spectroscopy at temperatures as low as 10 mK in an applied magnetic field to study the top layer of multilayer epitaxial graphene. When the Fermi level lies inside the fourfold Landau manifold, significant electron correlation effects result in an enhanced valley splitting for even filling factors, and an enhanced electron spin splitting for odd filling factors. Most unexpectedly, we observe states with Landau level filling factors of 7/2, 9/2 and 11/2, suggestive of new many-body states in graphene.

Structured epitaxial graphene: growth and properties

Graphene is generally considered to be a strong candidate to succeed silicon as an electronic material. However, to date, it actually has not yet demonstrated capabilities that exceed standard semiconducting materials. Currently demonstrated viable graphene devices are essentially limited to micrometre-sized ultrahigh-frequency analogue field effect transistors and quantum Hall effect devices for metrology. Nanoscopically patterned graphene tends to have disordered edges that severely reduce mobilities thereby obviating its advantage over other materials. Here we show that graphene grown on structured silicon carbide surfaces overcomes the edge roughness and promises to provide an inroad into nanoscale patterning of graphene. We show that high-quality ribbons and rings can be made using this technique. We also report on the progress towards high-mobility graphene monolayers on silicon carbide for device applications.

Top- and side-gated epitaxial graphene field effect transistors

Three types of first generation epitaxial graphene field effect transistors (FET) are presented and their relative merits are discussed. Graphene is epitaxially grown on both the carbon and silicon faces of hexagonal silicon carbide and patterned with electron beam lithography. The channels have a Hall bar geometry to facilitate magnetoresistance measurements. FETs patterned on the Si-face exhibit off-to-on channel resistance ratios that exceed 30. C-face FETs have lower off-to-on resistance ratios, but their mobilities (up to 5000 cm2/Vs) are much larger than that for Si-face transistors. Initial investigations into all-graphene side gate FET structures are promising.