Zelei Guo

Record maximum oscillation frequency in C-face epitaxial graphene transistors.

The maximum oscillation frequency (fmax) quantifies the practical upper bound for useful circuit operation. We report here an fmax of 70 GHz in transistors using epitaxial graphene grown on the C-face of SiC. This is a significant improvement over Si-face epitaxial graphene used in the prior high-frequency transistor studies, exemplifying the superior electronics potential of C-face epitaxial graphene. Careful transistor design using a high κ dielectric T-gate and self-aligned contacts further contributed to the record-breaking fmax.

Structured epitaxial graphene: growth and properties

Graphene is generally considered to be a strong candidate to succeed silicon as an electronic material. However, to date, it actually has not yet demonstrated capabilities that exceed standard semiconducting materials. Currently demonstrated viable graphene devices are essentially limited to micrometre-sized ultrahigh-frequency analogue field effect transistors and quantum Hall effect devices for metrology. Nanoscopically patterned graphene tends to have disordered edges that severely reduce mobilities thereby obviating its advantage over other materials. Here we show that graphene grown on structured silicon carbide surfaces overcomes the edge roughness and promises to provide an inroad into nanoscale patterning of graphene. We show that high-quality ribbons and rings can be made using this technique. We also report on the progress towards high-mobility graphene monolayers on silicon carbide for device applications.

Wafer bonding solution to epitaxial graphene?silicon integration

A new strategy for the integration of graphene electronics with silicon complementary metal–oxide–semiconductor (Si-CMOS) technology is demonstrated that requires neither graphene transfer nor patterning. Inspired by silicon-on-insulator and three-dimensional device hyper-integration techniques, a thin monocrystalline silicon layer ready for CMOS processing is bonded to epitaxial graphene (EG) on SiC. The parallel Si and graphene electronic platforms are interconnected by metal vias. In this method, EG is grown prior to bonding so that the process is compatible with EG high temperature growth and preserves graphene integrity and nano-structuring.

Planar edge Schottky barrier-tunneling transistors using epitaxial graphene/SiC junctions.

A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m.

Controlled epitaxial graphene growth within removable amorphous carbon corrals

We address the question of control of the silicon carbide (SiC) steps and terraces under epitaxial graphene on SiC and demonstrate amorphous carbon (aC) corrals as an ideal method to pin SiC surface steps. aC is compatible with graphene growth, structurally stable at high temperatures, and can be removed after graphene growth. For this, aC is first evaporated and patterned on SiC, then annealed in the graphene growth furnace. There at temperatures above 1200 °C, mobile SiC steps accumulate at the aC corral that provide effective step flow barriers. Aligned step free regions are thereby formed for subsequent graphene growth at temperatures above 1330 °C. Atomic force microscopy imaging supports the formation of step-free terraces on SiC with the step morphology aligned to the aC corrals. Raman spectroscopy indicates the presence of good graphene sheets on the step-free terraces.

Structured epitaxial graphene on SiC

We present recent results on epitaxial graphene high frequency FETs and a new concept of graphene nano-structuration. Nano-patterned epitaxial graphene grown on SiC is produced by etching the silicon carbide before annealing so that the graphene structures are produced in their final shapes. This avoids post-annealing patterning that is known to greatly affect transport properties on the nanoscale.