Yiming Liao

The energy distribution of NBTI-induced hole traps in the Si band gap in PNO pMOSFETs

By applying a low temperature sweeping technique, we indentify the energy profile of recoverable hole traps for nitrided oxide and SiO2 pMOSFETs subject to Negative Bias Temperature Stress (NBTS). It is found that the energy distribution of hole traps for nitrided oxide devices has two obvious peaks, one in the lower and one in the upper half of the silicon band gap. Both peaks gradually develop with increasing the stress time and temperature. We attempt to compare the energy profile for nitrided oxide and SiO2 devices to identify the nitrogen effect on the hole traps generated under NBTS.

The physical mechanisms of I G Random Telegraph Noise in deeply scaled pMOSFETs

The physical mechanism of I_G Random Telegraph Noise (I_G-RTN) has been studied in deeply scaled pMOSFETs subject to Negative Bias Temperature Stress (NBTS). Using carrier separation technique, we identify the majority carriers in I_G-RTN are channel holes. By investigating the electric field and temperature dependence of the capture time τ_c and emission time τ_e in I_G-RTN, it is found that the physical origin of I_G-RTN are NBTS-induced switching traps; Further quantitative analysis of I_G-V_G reveal that I_G-RTN is related to a tunneling process. Based on these results, we propose a tunneling model through NBTS-induced switching traps to explain the discrete gate leakage. The model provides a good agreement between the predicted and experimental data.

Physical understanding of negative bias temperature instability below room temperature

The physical mechanism of VT degradations under negative bias temperature stress below room temperature has been studied for SiO2 and plasma nitrided oxide (PNO-based) pMOSFETs. It is found that VT degradations in both devices exhibit strong dependence on the electric field and temperature. The analysis shows that this strong dependence follows multi-phonon field-assisted tunneling theory, which indicates the inelastic hole trapping mechanism in the low temperature negative bias temperature instability (NBTI). On the other hand, by applying a low temperature sweeping technique, the energy distribution of these NBTI-induced hole traps below room temperature is indentified. The energy distribution of hole traps has two obvious peaks, one in the lower and one in the upper half of the silicon band gap. Both peaks gradually develop with increasing the stress time and temperature. We attempt to compare the energy profile for SiO2 and PNO devices to identify the trap precursors in NBTI below room temperature.

Physical understanding of hot carrier injection variability in deeply scaled nMOSFETs

The saturation current variability σ(δIdsat) and lifetime variability in hot carrier injection (HCI) have been investigated for deeply scaled nMOSFETs. It is found that both of them are getting worse with scaling down. The statistical analysis of the large data sets from various CMOS sizes shows that σ(δIdsat) is dominated by the total number of Poisson-distributed defects generated by HCI stress and the length (L) and width (W) of these devices. We attempt to use a single parameter to accurately describe HCI variability in deeply scaled nMOSFETs.

CMOS NBTI degradation and recovery behaviors in a wide temperature range

Negative Bias Temperature (NBT) degradation in PMOS device with ultrathin SiON gate dielectric has been investigated at the temperature ranging from 218 K to 463 K. It is found that the degradation has different time-dependence behavior and activation energy above and below 268 K, evidencing two mechanisms in NBT degradation. One is related to interface state traps suggested in classic R-D model with neutral hydrogen atoms (H) as the diffusion species. The other is the hole trapping generation. The later dominates NBT degradation below 268 K. The possible hole trapping mechanism is proposed as inelastic hole tunneling and trapping into oxygen and nitrogen-related trap precursors under NBT stress.

A novel dual-frequency terahertz antenna in standard CMOS technology

A dual-frequency antenna resonated at 0.32 THz and 0.65 THz has been analyzed and simulated for CMOS THz imaging and sensing systems. It includes the two rectified bowtie structures designed at metal and poly-Si layers in standard CMOS technology. Simulation results show that the antenna has the high gain and radiation efficiency and a great impedance matching comparing to the conventional metal dual-band antenna. The demonstrated design opens a brand new way for ease realization of multi-band on-chip THz antenna in CMOS technologies.

Difference analysis method for negative bias temperature instability lifetime prediction in deeply scaled pMOSFETs

The fluctuation significantly affects the lifetime prediction of negative bias temperature instability (NBTI) for deeply scaled pMOSFETs. In this paper, we present a novel difference method to separate the time dependent fluctuation-related component from the NBTI quasi-static component in the threshold voltage shift. The extracted fluctuation-related component exhibits weak temperature and time dependences which is consistent with the characteristic of as-grown defect-induced trapping and detrapping while the quasi-static component presents electrical behaviors of generated-defect-induced NBTI degradation. On the basis of these results, a composite NBTI model is constructed and lifetime projection is derived for the small pMOSFETs.

Random telegraph noise on the threshold voltage of multi-level flash memory

We investigate the impact of random telegraph noise (RTN) on the threshold voltage of multi-level NOR flash memory. It is found that the threshold voltage variation () and the distribution due to RTN increase with the programmed level () of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

Performance enhancement of CMOS terahertz detector by drain current

In this paper, we study the effect of the drain current on terahertz detection for Si metal-oxide semiconductor field-effect transistors (MOSFETs) both theoretically and experimentally. The analytical model, which is based on the small-signal equivalent circuit of MOSFETs, predicts the significant improvement of the voltage responsivity R v with the bias current. The experiment on antennas integrated with MOSFETs agrees with the analytical model, but the R v improvement is accompanied first by a decrease, then an increase of the low-noise equivalent power (NEP) with the applied current. We determine the tradeoff between the low-NEP and high-R v for the current-biased detectors. As the best-case scenario, we obtained an improvement of about six times in R v without the cost of a higher NEP. We conclude that the current supply scheme can provide high-quality signal amplification in practical CMOS terahertz detection.

A novel antenna using high impedance surface resonance for THz imaging and sensing

A bowtie-shaped terahertz (THz) antenna with high impedance surface (HIS) is demonstrated for CMOS THz imaging and sensing systems. HIS is designed by metal layers in standard tail-end of CMOS technology and does not need any special post-process. We study the influence of HIS on antenna performance including the effect of metal vias and distance between antenna and HIS. A significant enhancement of the peak gain and a great impedance matching can be achieved by HIS with metal vias. It is found that the peak gain of the 0.65 THz antenna is significantly improved from 4.5dB to 9.1dB, against for the same antenna without HIS. The demonstrated design opens a way for the ease realization of high response on-chip THz detectors in CMOS technologies.